3D NAND Memory with Enhanced Switching Efficiency
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Summary
Problems
Existing 3D NAND memory systems require additional system management for erasing blocks due to dedicated memory cells at the ends of NAND strings, which complicates the programming and erasing processes.
Innovation solutions
The implementation of a 3D NAND memory system where each memory cell's floating gate is embedded by a socket component of a word line, reducing memory cell size and enhancing capacitive coupling, and using elongated polysilicon gates with metal strapping for source- and drain-side transistor switches to simplify switching operations.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If dedicated memory cells are placed near each end of the NAND string for switching, then switching function is achieved, but device complexity and system management requirements increase
Why choose this principle:
The patent merges the switching transistor gate with the word line structure. The elongated polysilicon gate of the switching transistor is formed as part of the word line, eliminating the need for separate dedicated switching memory cells. This integration reduces device complexity while maintaining the switching function through the capacitive coupling between the floating gate and the integrated word line gate.
Principle concept:
If dedicated memory cells are placed near each end of the NAND string for switching, then switching function is achieved, but device complexity and system management requirements increase
Why choose this principle:
The word line is given dual functionality: it serves both as the control line for memory cells and as the gate for switching transistors. The elongated polysilicon gate structure allows the word line to perform both read/write control and switching functions, reducing the need for additional dedicated components and simplifying system management.
Application Domain
Data Source
AI summary:
The implementation of a 3D NAND memory system where each memory cell's floating gate is embedded by a socket component of a word line, reducing memory cell size and enhancing capacitive coupling, and using elongated polysilicon gates with metal strapping for source- and drain-side transistor switches to simplify switching operations.
Abstract
A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.