Preventing Dishing in Bipolar Transistor Manufacturing
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Summary
Problems
The challenge in manufacturing bipolar transistors with wide emitter areas is the dishing effect during chemical mechanical polishing (CMP), which removes excess emitter material from inside the base window, limiting the achievable dimensions and affecting the reliability of RF signal handling in CMOS technology.
Innovation solutions
Incorporating polishing-resistant pillars within the base window to prevent excessive dishing during CMP, allowing for increased emitter dimensions without additional process steps, and using a layer stack including insulating, conductive, and protection layers like nitride to facilitate this.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the base window dimensions are increased to create wider emitter areas for handling large currents, then the current handling capability is improved, but the dishing effect during CMP becomes so pronounced that substantially all emitter material is removed from inside the base window
Why choose this principle:
A polishing-resistant layer is introduced as an intermediary element within the base window structure. This layer acts as a mediator during the CMP process, protecting the underlying emitter material from excessive removal while allowing the polishing process to proceed normally on surrounding areas. The polishing-resistant layer is strategically positioned to prevent the dishing effect from consuming all emitter material in wide base windows.
Principle concept:
If the base window dimensions are increased to create wider emitter areas for handling large currents, then the current handling capability is improved, but the dishing effect during CMP becomes so pronounced that substantially all emitter material is removed from inside the base window
Why choose this principle:
The polishing-resistant layer is deposited in advance before the CMP process to counteract the harmful dishing effect. By establishing this protective layer beforehand, the patent prevents the excessive removal of emitter material that would otherwise occur during polishing of wide base windows, thereby maintaining emitter dimensions within acceptable tolerances.
Application Domain
Data Source
AI summary:
Incorporating polishing-resistant pillars within the base window to prevent excessive dishing during CMP, allowing for increased emitter dimensions without additional process steps, and using a layer stack including insulating, conductive, and protection layers like nitride to facilitate this.
Abstract
Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.