Bypass Structure for Reliable CMOS-MEMS Integration
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Summary
Problems
Existing CMOS-MEMS integration methods face challenges in preventing charge accumulation during the etching process, which can damage the integrated circuit device due to the interconnection between the MEMS and CMOS devices, leading to issues like device drift, circuit leakage, and reduced reliability.
Innovation solutions
A bypass structure is introduced, utilizing a doped region with a lower pass-through voltage than the CMOS device, which acts as an electrical discharge path to prevent charge accumulation during the etching process, thereby isolating the MEMS device from the CMOS device and minimizing damage.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If MEMS device is processed last and interconnected to integrated circuit device before etching, then device integration and performance are improved, but charge accumulation during etching damages the integrated circuit device
Why choose this principle:
A bypass structure is introduced as an intermediary element between the MEMS device and the integrated circuit device. This bypass structure provides a dedicated charge dissipation path that mediates the harmful interaction during etching, allowing charge to be safely discharged without damaging the interconnected circuit devices.
Principle concept:
If MEMS device is processed last and interconnected to integrated circuit device before etching, then device integration and performance are improved, but charge accumulation during etching damages the integrated circuit device
Why choose this principle:
The interconnect structure is segmented into functional portions: a first portion interconnected to the integrated circuit device, a second portion forming the bypass structure, and a third portion interconnected to the MEMS device. This segmentation allows the bypass portion to handle charge dissipation separately from the signal transmission paths.
Application Domain
Data Source
AI summary:
A bypass structure is introduced, utilizing a doped region with a lower pass-through voltage than the CMOS device, which acts as an electrical discharge path to prevent charge accumulation during the etching process, thereby isolating the MEMS device from the CMOS device and minimizing damage.
Abstract
An apparatus including a bypass structure for complementary metal-oxide-semiconductor (CMOS) and/or microelectromechanical system (MEMS) devices, and method for fabricating such apparatus, is disclosed. An exemplary apparatus includes a first substrate; a second substrate that includes a MEMS device; an insulator disposed between the first substrate and the second substrate; and an electrical bypass structure disposed in the insulator layer that contacts a portion of the first substrate, wherein the electrical bypass structure is electrically isolated from the MEMS device in the second substrate and any device included in the first substrate.