Compact HBT Integration with Advanced CMOS Technologies
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Summary
Problems
Integration of heterojunction bipolar transistors (HBTs) with advanced CMOS technologies beyond 28 nm is challenging due to height limitations and complex, costly processes.
Innovation solutions
A method involving selective epitaxial growth of a SiGe film in a recess formed between isolation trenches on a silicon substrate, with a buried collector and emitter structure, reducing the overall height of the HBT device and simplifying the integration process.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If HBTs are integrated with advanced CMOS technologies (28 nm or beyond), then device integration capability is improved, but device height constraint is violated or process complexity increases
Why choose this principle:
The patent transitions from planar HBT structures to vertically-integrated structures where the HBT is formed within a recess in the CMOS substrate. This dimensional change allows the HBT to be embedded in the third dimension (depth), reducing the overall footprint and enabling better integration with advanced CMOS nodes while maintaining electrical performance.
Principle concept:
If HBTs are integrated with advanced CMOS technologies (28 nm or beyond), then device integration capability is improved, but device height constraint is violated or process complexity increases
Why choose this principle:
The HBT structure is nested within the CMOS device structure by forming the HBT in a recess of the substrate. The collector region extends into the recess, the base is formed at a higher level, and the emitter sits on top, creating a nested vertical configuration that integrates two device types in a compact arrangement.
Application Domain
Data Source
AI summary:
A method involving selective epitaxial growth of a SiGe film in a recess formed between isolation trenches on a silicon substrate, with a buried collector and emitter structure, reducing the overall height of the HBT device and simplifying the integration process.
Abstract
The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.