High-Density 3D ICs with Low-Temperature Layer Transfer
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Summary
Problems
Current methods for constructing three-dimensional integrated circuits (3D ICs) face challenges such as limited TSV density due to misalignment issues, high temperature requirements for transistor processing, and performance limitations from vertical transistors, which hinder the development of high-density, low-power, and cost-effective 3D ICs.
Innovation solutions
The method involves layer transfer techniques using ion-cut operations to form monolithic layers of transistors with through-layer vias (TLVs) of diameters less than 150 nm, allowing for high-density interconnects and the use of horizontally oriented transistors in mono-crystalline silicon, enabling low-temperature processing and integration of different transistor types like replacement-gate, FinFet, and double gate transistors.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If Through Silicon Vias (TSVs) are used to connect bonded wafers in 3D ICs, then electrical connections between layers are achieved, but the density of TSVs is limited due to large diameter requirements (one to ten microns) and misalignment issues
Why choose this principle:
The patent transitions from planar (2D) wafer bonding to three-dimensional (3D) stacking with vertically oriented transistors and interconnections. This dimensional change enables much higher interconnection density by utilizing the vertical dimension for both transistor orientation and interconnect routing, eliminating the need for large-diameter TSVs and achieving sub-100nm via dimensions.
Principle concept:
If Through Silicon Vias (TSVs) are used to connect bonded wafers in 3D ICs, then electrical connections between layers are achieved, but the density of TSVs is limited due to large diameter requirements (one to ten microns) and misalignment issues
Why choose this principle:
The patent segments the monolithic structure into multiple layers with intermediate transfer layers. This segmentation allows for better alignment control between layers, as each layer can be independently processed and aligned to the layer below it, rather than requiring precise alignment across the entire wafer thickness.
Application Domain
Data Source
AI summary:
The method involves layer transfer techniques using ion-cut operations to form monolithic layers of transistors with through-layer vias (TLVs) of diameters less than 150 nm, allowing for high-density interconnects and the use of horizontally oriented transistors in mono-crystalline silicon, enabling low-temperature processing and integration of different transistor types like replacement-gate, FinFet, and double gate transistors.
Abstract
An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.