Leadless Semiconductor Design for Low Inductance and High Reliability
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Summary
Problems
High inductance in gull wing leads of surface mount semiconductor packages for high power and high frequency applications leads to system performance issues due to noise and inductance, and high temperature bonding processes can damage leadframes in leadless packages.
Innovation solutions
A leadless semiconductor device with a thick heat sink flange and pre-formed frame structure having bent terminal pads, where semiconductor dies are attached using a high temperature bonding process, and the structure is encapsulated with the terminal pads exposed to reduce inductance and enhance reliability.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If gull wing leads are used in surface mount semiconductor packages, then the package can be easily manufactured and assembled, but the inductance increases leading to noise and performance degradation in high frequency applications
Why choose this principle:
The patent removes the traditional gull wing leads from the package structure entirely, replacing them with a leadless design where the terminal pads are directly exposed on the package bottom. This extraction of the problematic lead structure eliminates the source of inductance while maintaining manufacturing capability through standard encapsulation processes.
Principle concept:
If gull wing leads are used in surface mount semiconductor packages, then the package can be easily manufactured and assembled, but the inductance increases leading to noise and performance degradation in high frequency applications
Why choose this principle:
The invention transitions from a three-dimensional lead structure (gull wing leads extending outward) to a two-dimensional planar configuration where terminal pads lie flat on the package bottom surface. This dimensional change reduces the current path length and eliminates lead inductance, achieving lower inductance values suitable for high frequency applications.
Application Domain
Data Source
AI summary:
A leadless semiconductor device with a thick heat sink flange and pre-formed frame structure having bent terminal pads, where semiconductor dies are attached using a high temperature bonding process, and the structure is encapsulated with the terminal pads exposed to reduce inductance and enhance reliability.
Abstract
A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).