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Home»TRIZ Case»Magnetic Substructure Design for Reliable STT-RAM Performance

Magnetic Substructure Design for Reliable STT-RAM Performance

May 25, 20263 Mins Read
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Magnetic Substructure Design for Reliable STT-RAM Performance

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Summary

Problems

Conventional spin transfer torque random access memories (STT-RAMs) face high write error rates and lower magnetoresistance due to perpendicular magnetization orientation, which affects switching performance and scalability, and existing solutions to improve these issues often compromise energy consumption and thermal stability.

Innovation solutions

A magnetic junction with a pinned layer, a nonmagnetic spacer layer, and a free layer, where at least one of the layers includes a magnetic substructure composed of exchange-coupled magnetic layers interleaved with insertion layers such as Cr, Ta, Ti, W, Ru, V, Cu, Mg, or aluminum oxide, enhancing switching characteristics and thermal stability.

TRIZ Analysis

Specific contradictions:

write error rate
vs
device area

General conflict description:

Reliability
vs
Area of stationary object
TRIZ inspiration library
40 Composite materials
Try to solve problems with it

Principle concept:

If perpendicular magnetization orientation is used in STT-RAM, then write error rates increase and magnetoresistance decreases, but in-plane magnetization requires larger device area

Why choose this principle:

The patent employs composite magnetic layer structures with specific material combinations (e.g., CoFeB, CoFe, MgO) to achieve perpendicular magnetization with improved stability and reduced write error rates. The composite structure includes multiple magnetic layers with different properties working together to resolve the contradiction between reliability and area constraints

TRIZ inspiration library
35 Parameter changes
Try to solve problems with it

Principle concept:

If perpendicular magnetization orientation is used in STT-RAM, then write error rates increase and magnetoresistance decreases, but in-plane magnetization requires larger device area

Why choose this principle:

The patent changes key magnetic parameters including magnetization orientation (from in-plane to perpendicular), anisotropy energy, and layer thicknesses to optimize both write error rate and device area. By adjusting these parameters, the invention achieves perpendicular magnetization that reduces write error rates without requiring excessive device area

Application Domain

stt-ram magnetic substructure thermal stability

Data Source

Patent US8432009B2 Method and system for providing magnetic layers having insertion layers for use in spin transfer torque memories
Publication Date: 30 Apr 2013 TRIZ 电器元件
FIG 01
US08432009-D00000
FIG 02
US08432009-D00001
FIG 03
US08432009-D00002
Login to view Image

AI summary:

A magnetic junction with a pinned layer, a nonmagnetic spacer layer, and a free layer, where at least one of the layers includes a magnetic substructure composed of exchange-coupled magnetic layers interleaved with insertion layers such as Cr, Ta, Ti, W, Ru, V, Cu, Mg, or aluminum oxide, enhancing switching characteristics and thermal stability.

Abstract

A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the pinned layer and the free layer includes a magnetic substructure. The magnetic substructure includes at least two magnetic layers interleaved with at least one insertion layer. Each insertion layer includes at least one of Cr, Ta, Ti, W, Ru, V, Cu, Mg, aluminum oxide, and MgO. The magnetic layers are exchange coupled.

Contents

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    magnetic substructure stt-ram thermal stability
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    Table of Contents
    • Magnetic Substructure Design for Reliable STT-RAM Performance
      • Summary
      • TRIZ Analysis
      • Data Source
      • Accelerate from idea to impact
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