Reducing Resistance in Memory Arrays with Metal-Enhanced Access Lines
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Summary
Problems
Existing memory arrays face challenges in reducing electrical resistance along buried access lines, which affects performance and density, as conductively-doped semiconductor materials have lower conductivity compared to metal materials, leading to inefficiencies in memory cell operations.
Innovation solutions
The use of higher conductivity metal materials, such as metal silicides, directly against the tops of buried access lines and extending between pillars, reduces electrical resistance and increases the number of memory cells that can be placed between conductive vias, enhancing circuit density and performance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If conductively-doped semiconductor material is used for buried access lines, then the memory array can be fabricated with standard semiconductor processes, but the electrical resistance along the access lines is high which limits performance and density
Why choose this principle:
The patent applies composite materials by combining conductively-doped semiconductor material with metal materials (such as metal silicide) to form buried access lines. The metal material is deposited over the semiconductor substrate and selectively removed in pillar regions, creating a composite structure that leverages the high conductivity of metal while maintaining compatibility with semiconductor fabrication processes. This resolves the contradiction by achieving low resistance (improving reliability) through material composition rather than process complexity.
Principle concept:
If more memory cells are placed between conductive vias, then the memory array density increases, but the resistance along the access lines increases which degrades performance
Why choose this principle:
The patent changes the physical parameter of the access line material from purely semiconductor-based to metal-enhanced composite material. This parameter change (material composition) directly reduces electrical resistance, enabling higher memory cell density between vias without the performance degradation that would normally result from increased access line length and resistance.
Application Domain
Data Source
AI summary:
The use of higher conductivity metal materials, such as metal silicides, directly against the tops of buried access lines and extending between pillars, reduces electrical resistance and increases the number of memory cells that can be placed between conductive vias, enhancing circuit density and performance.
Abstract
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.