Preventing Shorts in Memory Arrays with Layered Insulation
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Summary
Problems
In the formation of memory arrays, particularly in NAND architecture, there is a challenge in preventing fatal shorts during the etching process due to mis-aligned masks and shared material compositions, which can lead to electrical shorts when forming conductive vias and wordlines.
Innovation solutions
The method involves forming a memory array with vertically-alternating insulative and conductive tiers, where channel-material strings project upwardly from the uppermost tier, and a first insulator material is deposited above these strings. This configuration ensures that conductive vias can be directly electrically coupled to the channel-material strings without shared material compositions causing shorts, using etching chemistries that selectively remove materials to prevent over-etching and shorts.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a single insulator material is used above the uppermost tier, then the process is simpler, but fatal shorts occur due to over-etching and mis-aligned masks
Why choose this principle:
The insulator material above the uppermost tier is segmented into two distinct layers: a first insulator material layer and a second insulator material layer. This segmentation allows each layer to serve specific functions – the first layer provides a buffer zone that prevents over-etching from reaching the channel-material strings, while the second layer provides additional insulation. This resolves the contradiction by maintaining process simplicity through a systematic layered approach while dramatically improving reliability by preventing fatal shorts.
Principle concept:
If a single insulator material is used above the uppermost tier, then the process is simpler, but fatal shorts occur due to over-etching and mis-aligned masks
Why choose this principle:
The first insulator material layer is deposited as a preliminary protective layer before the second insulator material layer. This preliminary action creates a buffer zone that prevents the etching process from penetrating too deeply and causing shorts to the channel-material strings. The preliminary insulator layer is strategically positioned to intercept potential over-etching damage before it can reach critical conductive elements.
Application Domain
Data Source
AI summary:
The method involves forming a memory array with vertically-alternating insulative and conductive tiers, where channel-material strings project upwardly from the uppermost tier, and a first insulator material is deposited above these strings. This configuration ensures that conductive vias can be directly electrically coupled to the channel-material strings without shared material compositions causing shorts, using etching chemistries that selectively remove materials to prevent over-etching and shorts.
Abstract
A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.