Optimizing Metal Gate Structures for Advanced MOS Devices
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Summary
Problems
As semiconductor technologies advance, the miniaturization of integrated circuits increases complexity in fabricating metal gate structures for MOS devices, particularly in achieving thin, uniform metal sidewalls for both short and long channel MOS devices, which affects electrical performance.
Innovation solutions
The use of physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes to form metal interior layers and dielectric layers, combined with etch-back techniques and protection layers, allows for the creation of thin, uneven metal sidewalls and corner step regions, optimizing metal gate structure fabrication for both short and long channel MOS devices.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes are used to deposit metal materials, then the gate terminal resistance is reduced and propagation delay is improved, but the fabrication complexity increases due to the need for precise control of metal sidewall thickness and uniformity
Why choose this principle:
The gate structure is segmented into multiple functional layers: a metal interior layer for electrical conductivity, dielectric layers for insulation and spacing, and protection layers for structural support. This segmentation allows each layer to be optimized independently for its specific function, reducing the interdependence that causes fabrication complexity.
Principle concept:
If physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes are used to deposit metal materials, then the gate terminal resistance is reduced and propagation delay is improved, but the fabrication complexity increases due to the need for precise control of metal sidewall thickness and uniformity
Why choose this principle:
The dielectric layer is formed on the sidewalls and bottom of the trench before the metal layer is deposited. This preliminary action creates a predefined geometry that guides subsequent metal deposition, ensuring uniform metal sidewall thickness without requiring complex real-time control during metal fabrication.
Application Domain
Data Source
AI summary:
The use of physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes to form metal interior layers and dielectric layers, combined with etch-back techniques and protection layers, allows for the creation of thin, uneven metal sidewalls and corner step regions, optimizing metal gate structure fabrication for both short and long channel MOS devices.
Abstract
A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall.