Negative-Capacitance FET Design for Faster Switching
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Summary
Problems
Conventional semiconductor integrated circuits face challenges in scaling down due to increased complexity and design manufacturing issues, particularly in achieving efficient and fast transistors with reduced leakage and improved current flow.
Innovation solutions
The integration of multiple ferroelectric layers in FinFETs, where a first ferroelectric layer is epitaxially formed on the fin active region and a second ferroelectric layer is in physical contact with the gate electrode, producing a hysteresis-free or substantially hysteresis-free field effect transistor (FET) with negative gate capacitance, reducing subthreshold swing and power consumption.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If conventional FET scaling is pursued, then device density increases, but leakage current increases and switching speed decreases
Why choose this principle:
The patent changes the electrical parameters of the gate structure by introducing ferroelectric materials with negative capacitance, transforming the gate's electrical characteristics to achieve sub-60mV/dec subthreshold swing and reduced leakage current while maintaining high device density
Principle concept:
If conventional FET scaling is pursued, then device density increases, but leakage current increases and switching speed decreases
Why choose this principle:
The patent employs composite gate structures combining ferroelectric materials (e.g., HfO2, Pb(Zr,Ti)O3) with metal layers or semiconductors to create negative capacitance FETs that simultaneously achieve high density and low leakage through the synergistic properties of the composite materials
Application Domain
Data Source
AI summary:
The integration of multiple ferroelectric layers in FinFETs, where a first ferroelectric layer is epitaxially formed on the fin active region and a second ferroelectric layer is in physical contact with the gate electrode, producing a hysteresis-free or substantially hysteresis-free field effect transistor (FET) with negative gate capacitance, reducing subthreshold swing and power consumption.
Abstract
Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.