Place-Efficient Capacitor Design for High Integration Density
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Summary
Problems
Existing integrated circuits face challenges in achieving high capacitance per unit area for capacitors without increasing chip area or size, which limits integration density and competes with other semiconductor devices.
Innovation solutions
The method involves forming etch-resistant particles as a porosity mask to extend the surface area of dielectric layers between capacitor electrodes, increasing the effective area without occupying more space, by etching the dielectric layer using these particles as an etch mask and filling the extended openings with conductive material.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the area of capacitor electrodes is increased to achieve high capacitance, then capacitance is improved, but chip area occupied by the capacitor increases
Why choose this principle:
The patent transitions from a two-dimensional electrode surface to a three-dimensional porous structure. By forming a dielectric layer with controlled porosity (30-70% pore volume) and coating the internal surfaces of pores with conductive material, the electrode surface area is dramatically increased within the same footprint, achieving high capacitance without increasing chip area
Principle concept:
If the area of capacitor electrodes is increased to achieve high capacitance, then capacitance is improved, but chip area occupied by the capacitor increases
Why choose this principle:
The patent utilizes a porous dielectric layer as the core structure. The porous material provides extensive internal surface area that can be coated with conductive material to form three-dimensional electrode networks. The porosity (30-70% void volume) enables significantly increased surface area compared to solid dielectric structures, directly resolving the contradiction between capacitance and chip area
Application Domain
Data Source
AI summary:
The method involves forming etch-resistant particles as a porosity mask to extend the surface area of dielectric layers between capacitor electrodes, increasing the effective area without occupying more space, by etching the dielectric layer using these particles as an etch mask and filling the extended openings with conductive material.
Abstract
Integrated circuits having place-efficient capacitors and methods for fabricating the same are provided. A dielectric layer is formed overlying a conductive feature on a semiconductor substrate. A via opening is formed into the dielectric layer to expose a portion of the conductive feature. A partial opening is etched into the dielectric layer and positioned over the conductive feature. Etch resistant particles are deposited overlying the dielectric layer and in the partial opening. The dielectric layer is further etched using the etch resistant particles as an etch mask to extend the partial opening. A first conductive layer is formed overlying the extended partial opening and electrically contacting the conductive feature. A capacitor insulating layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the insulating layer.