Reducing Distortion in PLL Frequency Synthesizers with Patent-Based Solutions
Here’s PatSnap Eureka !
Summary
Problems
Conventional PLL frequency synthesizers suffer from distortion, noise, and timing errors due to the implementation of frequency regenerators, which can violate transmission specifications.
Innovation solutions
A phase locked loop frequency synthesizer is designed with a frequency regenerator and a modulation processor that compensates for distortion induced by the frequency regenerator, using a digitally processed input modulation signal to adjust the division factor of the frequency dividing unit and implement a regenerator compensator to ensure the modulation index and timing performance meet transmission specifications.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a frequency regenerator is implemented in the PLL frequency synthesizer, then the output frequency range is extended and flexibility is improved, but distortion, noise, and timing errors are introduced that violate transmission specifications
Why choose this principle:
The system performs preliminary distortion compensation by processing the modulation signal before it enters the frequency regenerator. The compensation filter pre-corrects the modulation index distortion that will be introduced by the frequency divider, ensuring that the final output meets transmission specifications despite the regenerator being present
Principle concept:
If a frequency regenerator is implemented in the PLL frequency synthesizer, then the output frequency range is extended and flexibility is improved, but distortion, noise, and timing errors are introduced that violate transmission specifications
Why choose this principle:
The system uses feedback mechanisms to monitor and adjust the modulation signal characteristics. By measuring the actual distortion introduced by the frequency regenerator and feeding this information back to the compensation filter, the system dynamically adjusts the compensation parameters to maintain specification compliance
Application Domain
Data Source
AI summary:
A phase locked loop frequency synthesizer is designed with a frequency regenerator and a modulation processor that compensates for distortion induced by the frequency regenerator, using a digitally processed input modulation signal to adjust the division factor of the frequency dividing unit and implement a regenerator compensator to ensure the modulation index and timing performance meet transmission specifications.
Abstract
A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator. The modulation processor generates the processed input modulation signal to adjust the division factor of the frequency dividing unit and compensating for distortion induced by the frequency regenerator.