Enhanced Polymer Thickness for Semiconductor Stress Buffering
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Summary
Problems
The high mismatch in coefficients of thermal expansion between solder bumps, semiconductor dies, and chip package substrates leads to thermal stresses and potential breakage of back-end-of-the-line material due to rotational forces on solder bumps during thermal cycling.
Innovation solutions
A topographical feature is introduced on the semiconductor die surface near the conductive bond pads, creating a gap that enhances the thickness of the non-conductive layer, providing a stress buffer and preventing breakage at high stress areas.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the non-conductive layer thickness is increased to provide stress buffering, then reliability improves, but device complexity increases
Why choose this principle:
The patent applies local quality by creating a topographical feature that locally increases the non-conductive layer thickness only in specific high-stress areas (under and around solder bumps), rather than uniformly increasing thickness across the entire die. This localized approach provides stress buffering where needed while avoiding unnecessary complexity and material usage in low-stress regions.
Principle concept:
If the non-conductive layer thickness is increased to provide stress buffering, then reliability improves, but device complexity increases
Why choose this principle:
The patent introduces a vertical dimensionality change by forming a topographical feature (such as a raised ridge or mound) on the die surface. This three-dimensional structure allows the non-conductive layer to have variable thickness, creating an enhanced stress buffer zone vertically under the solder bumps without increasing the lateral footprint or overall device complexity.
Application Domain
Data Source
AI summary:
A topographical feature is introduced on the semiconductor die surface near the conductive bond pads, creating a gap that enhances the thickness of the non-conductive layer, providing a stress buffer and preventing breakage at high stress areas.
Abstract
A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.