Read Latency Control with Minimal Circuit Complexity
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Summary
Problems
High-speed DRAMs face challenges in maintaining precise read latency due to indeterminable read clock delay relative to read data valid time, leading to difficulties in ensuring correct data output and specified read latency, which is exacerbated by the need for large and cumbersome DLL circuits that consume valuable chip space.
Innovation solutions
A read latency control circuit utilizing a synchronization circuit to generate internal clock signals that synchronize read data with an external clock signal, eliminating the need for additional circuitry like slave delay circuits by using upstream and downstream clock signals to track clock pulses and achieve the specified read latency.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a DLL circuit is used to generate internal clock signals for synchronizing read data with external clock, then read latency control is improved, but chip area consumption increases due to large and cumbersome DLL circuits
Why choose this principle:
The patent extracts the essential timing control function from the traditional DLL circuit by using a minimal delay element (single inverter or buffer) to generate the read clock signal. This extraction removes the cumbersome DLL circuitry while retaining the core functionality of synchronizing read data with the external clock signal, thereby reducing chip area while maintaining read latency precision.
Principle concept:
If a DLL circuit is used to generate internal clock signals for synchronizing read data with external clock, then read latency control is improved, but chip area consumption increases due to large and cumbersome DLL circuits
Why choose this principle:
The patent creates a simplified copy of the DLL timing control mechanism by using a delay element that replicates the essential phase adjustment function. Instead of implementing a full DLL circuit, a single delay element copies the necessary timing relationship between external clock and read data, achieving the same synchronization effect with minimal area overhead.
Application Domain
Data Source
AI summary:
A read latency control circuit utilizing a synchronization circuit to generate internal clock signals that synchronize read data with an external clock signal, eliminating the need for additional circuitry like slave delay circuits by using upstream and downstream clock signals to track clock pulses and achieve the specified read latency.
Abstract
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.