Reducing Leak Current in Semiconductor Circuits with Data Integrity
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Summary
Problems
Conventional semiconductor integrated circuits face challenges in reducing leak current while maintaining data integrity in standby mode, with existing techniques either erasing data or increasing circuit complexity and parasitic capacity.
Innovation solutions
A semiconductor integrated circuit design that separates logic circuits into data non-holding and data holding circuits, using virtual high potential source lines and switches to manage substrate potentials, allowing for reduced leak current and reliable data retention with a simple circuit configuration.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the power switch (high threshold MOS transistor) is turned off to reduce leak current in standby mode, then power consumption is reduced, but data retained in the logic circuit is erased
Why choose this principle:
The logic circuit is divided into two separate circuits: a data non-holding circuit for operations that do not require data retention, and a data holding circuit for operations that require data retention in standby mode. This segmentation allows each circuit to be optimized independently for its specific function.
Principle concept:
If the power switch (high threshold MOS transistor) is turned off to reduce leak current in standby mode, then power consumption is reduced, but data retained in the logic circuit is erased
Why choose this principle:
Different substrate potentials are applied to different parts of the circuit. The data holding circuit receives a first substrate potential that maintains data retention, while the data non-holding circuit receives a second substrate potential optimized for leak current reduction. This local differentiation resolves the contradiction by providing appropriate conditions to each circuit segment.
Application Domain
Data Source
AI summary:
A semiconductor integrated circuit design that separates logic circuits into data non-holding and data holding circuits, using virtual high potential source lines and switches to manage substrate potentials, allowing for reduced leak current and reliable data retention with a simple circuit configuration.
Abstract
The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.