Reducing Parasitic Inductance in Semiconductor Devices
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Summary
Problems
The parasitic inductance of the emitter or source in semiconductor devices degrades the gain and band characteristics of power amplifiers, particularly at higher operating frequencies, necessitating a reduction in self-inductance to improve performance.
Innovation solutions
The semiconductor device incorporates a ground bump disposed near the transistor to reduce the self-inductance of the current path, with additional output bumps positioned such that their geometric centers form a polygon enclosing the ground bump's center, thereby minimizing parasitic inductance by canceling magnetic fluxes.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a ground bump is disposed near the transistor to reduce parasitic inductance, then the self-inductance of the current path is reduced, but the geometric arrangement becomes more complex
Why choose this principle:
The patent employs asymmetric arrangement of bumps where the ground bump is positioned at a specific asymmetric location relative to the transistor, and output bumps are arranged in a polygon configuration. This asymmetric geometry optimizes the cancellation of magnetic flux while maintaining manufacturability, resolving the contradiction between reducing parasitic inductance and avoiding excessive complexity
Principle concept:
If a ground bump is disposed near the transistor to reduce parasitic inductance, then the self-inductance of the current path is reduced, but the geometric arrangement becomes more complex
Why choose this principle:
The patent transitions from considering only the proximity distance (one dimension) to utilizing the two-dimensional planar arrangement of bumps. By positioning the ground bump's geometric center inside the polygon formed by output bumps in the planar dimension, the solution optimizes parasitic inductance reduction through geometric configuration rather than merely minimizing distance
Application Domain
Data Source
AI summary:
The semiconductor device incorporates a ground bump disposed near the transistor to reduce the self-inductance of the current path, with additional output bumps positioned such that their geometric centers form a polygon enclosing the ground bump's center, thereby minimizing parasitic inductance by canceling magnetic fluxes.
Abstract
A semiconductor device includes at least one transistor disposed on or in a substrate. The transistor is a bipolar transistor including an emitter, a base, and a collector, or a field-effect transistor including a source, a gate, and a drain. At least one first bump connected to the emitter or the source is disposed on the substrate. Furthermore, at least three second bumps connected to the collector or the drain are disposed on the substrate. In plan view, a geometric center of the at least one first bump is located inside a polygon whose vertices correspond to geometric centers of the at least three second bumps.