Self-Aligned Contact Formation for Semiconductor Miniaturization
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Summary
Problems
The miniaturization of semiconductor memory devices is limited by the requirement of a minimum distance between contacts and local interconnects to prevent shorting, which increases the size of memory cells and affects device density, especially as feature sizes scale down to sub-quarter micron levels.
Innovation solutions
A method involving the formation of an etch stop layer and a first dielectric layer with a thickness greater than the multi-layer structures and etch stop layer, allowing simultaneous patterning and filling of contacts and local interconnects, followed by chemical mechanical polishing to reduce excess material and relax the minimal spacing requirement, enabling easier patterning and improved isolation.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a minimum distance is maintained between contacts and local interconnects to prevent shorting, then electrical reliability is improved, but device area increases and density decreases
Why choose this principle:
The patent transitions from planar patterning to three-dimensional self-aligned formation. Contacts and local interconnects are formed in different vertical levels with precise lateral alignment achieved through sidewall spacer structures, eliminating the need for horizontal spacing while maintaining electrical isolation.
Principle concept:
If a minimum distance is maintained between contacts and local interconnects to prevent shorting, then electrical reliability is improved, but device area increases and density decreases
Why choose this principle:
Sidewall spacer structures serve as intermediary elements that define the lateral boundaries of contacts and local interconnects. These spacers act as self-aligned masks during etching processes, ensuring precise positioning without requiring additional spacing between features.
Application Domain
Data Source
AI summary:
A method involving the formation of an etch stop layer and a first dielectric layer with a thickness greater than the multi-layer structures and etch stop layer, allowing simultaneous patterning and filling of contacts and local interconnects, followed by chemical mechanical polishing to reduce excess material and relax the minimal spacing requirement, enabling easier patterning and improved isolation.
Abstract
The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.