Semiconductor Device Design for High Withstand Voltage
Here’s PatSnap Eureka !
Summary
Problems
Current semiconductor devices with LDMOSFETs using thick film SOI substrates face challenges in maintaining high withstand voltage while minimizing the semiconductor layer thickness, as decreasing impurity concentration in the drift region leads to increased depletion layer extension and capacitance reduction, making it difficult to manufacture deep trenches and achieve desired voltage levels.
Innovation solutions
Incorporating a first conductive type region with a higher impurity concentration than the semiconductor layer but lower than the drain region, positioned deeper than the drain region, to suppress depletion layer extension towards the drain, allowing for a thinner semiconductor layer without compromising withstand voltage, thereby simplifying the manufacturing process.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the impurity concentration of the drift region is decreased to increase withstand voltage, then the withstand voltage increases, but the depletion layer extends greatly toward the drain region and the SOI layer must be made large in layer thickness
Why choose this principle:
The patent applies local quality by creating an N-type region with intermediate impurity concentration (1×10^16 to 1×10^18 atoms/cm³) specifically in the drift region beneath the drain region. This localized variation in impurity concentration allows the depletion layer to terminate at the boundary of this N-type region, preventing excessive extension toward the drain while maintaining high withstand voltage. The different impurity concentrations in different regions (low in drift region, intermediate in N-type region, high in drain region) resolve the contradiction between withstand voltage and layer thickness.
Principle concept:
If the impurity concentration of the drift region is decreased to increase withstand voltage, then the withstand voltage increases, but the depletion layer extends greatly toward the drain region and the SOI layer must be made large in layer thickness
Why choose this principle:
The patent changes the impurity concentration parameter vertically through the drift region by introducing an N-type region with intermediate impurity concentration between the low-concentration drift region and the high-concentration drain region. This parameter change creates an impurity concentration gradient that controls the depletion layer width and termination point, enabling high withstand voltage with reduced SOI layer thickness.
Application Domain
Data Source
AI summary:
Incorporating a first conductive type region with a higher impurity concentration than the semiconductor layer but lower than the drain region, positioned deeper than the drain region, to suppress depletion layer extension towards the drain, allowing for a thinner semiconductor layer without compromising withstand voltage, thereby simplifying the manufacturing process.
Abstract
A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region.