Reducing Yield Loss in Semiconductor Etching with Dielectric Layers
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Summary
Problems
The challenge in semiconductor chip fabrication is the re-deposition of conductive material onto sidewalls and upper surfaces during plasma etching, which affects etching rates and increases costs due to the need for waferless auto-clean processes, leading to yield loss and RC delay in integrated chips.
Innovation solutions
A multilayer stack upper conductive structure is formed with a dielectric layer between the first and second conductive layers, preventing plasma from bombarding the first conductive layer and thus reducing re-deposition of conductive material, facilitating accurate removal of metal oxides and maintaining etching rates.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If plasma etching is used to form the upper conductive structure, then etching precision and speed are improved, but conductive material re-deposits onto sidewalls and upper surfaces causing yield loss and RC delay
Why choose this principle:
A dielectric layer is introduced as an intermediary between the first conductive layer and the plasma etching environment. This dielectric layer acts as a protective barrier that prevents conductive material from re-depositing onto sidewalls and upper surfaces during plasma etching, thereby eliminating yield loss and RC delay while maintaining etching precision
Principle concept:
If plasma etching is used to form the upper conductive structure, then etching precision and speed are improved, but conductive material re-deposits onto sidewalls and upper surfaces causing yield loss and RC delay
Why choose this principle:
The dielectric layer is formed in advance before plasma etching to preemptively prevent the harmful re-deposition of conductive material. This preliminary protective action stops the problem before it occurs, allowing plasma etching to proceed without causing yield loss or RC delay
Application Domain
Data Source
AI summary:
A multilayer stack upper conductive structure is formed with a dielectric layer between the first and second conductive layers, preventing plasma from bombarding the first conductive layer and thus reducing re-deposition of conductive material, facilitating accurate removal of metal oxides and maintaining etching rates.
Abstract
Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.