Reducing Residue in Semiconductor Etching with Step Reduction Patterns
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Summary
Problems
The conventional method of manufacturing flash memory devices results in residue formation during the anisotropic etching process, which blocks dopant implantation and increases the resistance of the word line, leading to delays in data writing.
Innovation solutions
A semiconductor device design that includes a step reduction pattern on the conductive pattern, which prevents residue formation during etching and allows for uniform dopant implantation, thereby reducing word line resistance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If anisotropic etching is performed to form sidewall spacers, then the sidewall spacer structure is formed, but residue forms at the step which blocks dopant implantation and increases word line resistance
Why choose this principle:
A step reduction pattern is formed on the conductive pattern before the anisotropic etching process. This preliminary structural modification creates a gradual height decrease that prevents residue formation during subsequent etching, allowing dopant implantation to proceed uniformly without blockage.
Principle concept:
If anisotropic etching is performed to form sidewall spacers, then the sidewall spacer structure is formed, but residue forms at the step which blocks dopant implantation and increases word line resistance
Why choose this principle:
The conductive pattern is modified locally by forming a step reduction pattern at specific regions where residue tends to accumulate. This creates different surface heights in different areas, with the stepped portion having gradually decreasing height to prevent residue formation while maintaining the original structure in other areas.
Application Domain
Data Source
AI summary:
A semiconductor device design that includes a step reduction pattern on the conductive pattern, which prevents residue formation during etching and allows for uniform dopant implantation, thereby reducing word line resistance.
Abstract
A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over the plurality of first conductive patterns and the second conductive pattern, and a third conductive pattern formed over the first insulation film.