Reducing On-Resistance in Semiconductor Devices with Etch Stop Layers
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Summary
Problems
The increasing demand for smaller, lighter, and more powerful electronic devices with higher power densities, particularly in electrical converter devices, necessitates the minimization of energy losses due to electrical resistances, which is challenging in existing semiconductor manufacturing processes.
Innovation solutions
A method for manufacturing semiconductor devices involves selectively removing semiconductor chips at one main face to reduce thickness, using techniques like etching with an etch stop layer and encapsulation, while maintaining structural integrity and functionality, particularly for vertical power transistors, to decrease on-resistance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the semiconductor chip thickness is reduced to decrease on-resistance, then the on-resistance decreases and energy conversion efficiency improves, but the structural integrity and mechanical strength of the device deteriorate
Why choose this principle:
An etch stop layer is formed at a predetermined depth within the semiconductor chip before any thinning operations. This pre-formed layer acts as a mechanical reinforcement that prevents the chip from becoming too thin and losing structural integrity, while still allowing the chip to be thinned enough to reduce on-resistance.
Principle concept:
If the semiconductor chip thickness is reduced to decrease on-resistance, then the on-resistance decreases and energy conversion efficiency improves, but the structural integrity and mechanical strength of the device deteriorate
Why choose this principle:
The etch stop layer serves as an intermediary structural element between the front and back surfaces of the semiconductor chip. It provides mechanical support and prevents through-etching or excessive thinning, enabling the chip to maintain sufficient strength while being thinned to reduce resistance.
Application Domain
Data Source
AI summary:
A method for manufacturing semiconductor devices involves selectively removing semiconductor chips at one main face to reduce thickness, using techniques like etching with an etch stop layer and encapsulation, while maintaining structural integrity and functionality, particularly for vertical power transistors, to decrease on-resistance.
Abstract
The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.