Semiconductor Passivation for Contamination-Free Manufacturing
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Summary
Problems
In semiconductor device manufacturing, the exposure of copper alignment marks in the scribe lane during passivation film removal leads to potential contamination of equipment and process defects, due to increased parasitic capacitance and resistance in highly integrated devices.
Innovation solutions
A method involving sequential deposition of passivation films with differing etching selectivities, where a first passivation film protects the copper alignment mark, and a second and third passivation film are selectively removed in the scribe lane to prevent exposure, using a damascene process and photolithographic techniques.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the passivation film in the scribe lane is removed to prevent stress defects, then the reliability of the device is improved, but the copper alignment mark becomes exposed causing contamination of equipment and process environment
Why choose this principle:
The passivation film structure is segmented into multiple layers with different etching selectivities. The first passivation film has high etching selectivity relative to the second passivation film, allowing selective removal of the second film in the scribe lane while the first film remains to protect the copper alignment mark. This segmentation enables different regions of the device to have different passivation configurations tailored to their specific needs.
Principle concept:
If the passivation film in the scribe lane is removed to prevent stress defects, then the reliability of the device is improved, but the copper alignment mark becomes exposed causing contamination of equipment and process environment
Why choose this principle:
The patent applies local quality by providing different passivation film configurations in different regions. In the chip area, both first and second passivation films are present for comprehensive protection. In the scribe lane, only the first passivation film is retained after selective removal of the second film, providing sufficient protection for the copper alignment mark while preventing stress defects during dicing.
Application Domain
Data Source
AI summary:
A method involving sequential deposition of passivation films with differing etching selectivities, where a first passivation film protects the copper alignment mark, and a second and third passivation film are selectively removed in the scribe lane to prevent exposure, using a damascene process and photolithographic techniques.
Abstract
A semiconductor device and a method manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.