Efficient SOI Device Design with Contact Trenches
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Summary
Problems
SOI devices face challenges with significant area consumption due to wide trenches for contact formation, which increases device size, and are not well-suited for integrating both high-voltage and low-voltage components effectively, with potential performance impairment from impurities in the active layer.
Innovation solutions
The method involves forming one or more contact trenches across the insulating layer before epitaxial growth, using tilted impurity implantation to create a high-dopant interface region that fills the trenches with semiconductor material, allowing for efficient front-rear contact formation and impurity gettering, while maintaining the SOI structure for high-voltage components and using PN-junction insulation for low-voltage components.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If wide trenches are used for contact formation to ensure conformal conductive layer coverage, then contact reliability is improved, but device area increases significantly
Why choose this principle:
The patent performs preliminary actions by forming contact trenches through the insulating layer before epitaxial growth, and by pre-defining conductor pattern regions. This allows the conductive layer to be deposited conformally on pre-formed trench walls, ensuring reliable contact without requiring excessively wide trenches, thus resolving the contradiction between contact reliability and device area.
Principle concept:
If wide trenches are used for contact formation to ensure conformal conductive layer coverage, then contact reliability is improved, but device area increases significantly
Why choose this principle:
The patent segments the device structure into distinct regions: contact trenches for vertical connections, conductor pattern regions for horizontal connections, and active regions for device operation. This segmentation allows each region to be optimized independently, enabling narrow trenches that ensure conformal coverage while minimizing the overall device footprint.
Application Domain
Data Source
AI summary:
The method involves forming one or more contact trenches across the insulating layer before epitaxial growth, using tilted impurity implantation to create a high-dopant interface region that fills the trenches with semiconductor material, allowing for efficient front-rear contact formation and impurity gettering, while maintaining the SOI structure for high-voltage components and using PN-junction insulation for low-voltage components.
Abstract
A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.