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Home»TRIZ Case»Sub-Resolution Feature Formation in Semiconductor Devices

Sub-Resolution Feature Formation in Semiconductor Devices

May 25, 20263 Mins Read
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Sub-Resolution Feature Formation in Semiconductor Devices

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Summary

Problems

Conventional photolithography techniques have limitations in forming features with dimensions below a certain critical size due to optics limitations and wavelength constraints, making it difficult to achieve smaller pitch and critical dimensions in semiconductor devices.

Innovation solutions

The anti-spacer process is employed, which involves chemically modifying the outer portions of photosensitive materials to make them soluble, forming filler materials between them, and removing these portions to create trenches and openings, allowing for the formation of features with smaller dimensions by extending holes into the substrate, thereby reducing the complexity and cost compared to conventional pitch multiplication techniques.

TRIZ Analysis

Specific contradictions:

critical dimension
vs
feature formation reliability

General conflict description:

Manufacturing precision
vs
Reliability
TRIZ inspiration library
1 Segmentation
Try to solve problems with it

Principle concept:

If conventional photolithography techniques are used, then features can be formed with standard dimensions, but features with critical dimensions below 37.5 nm cannot be reliably formed due to optics limitations and radiation wavelength constraints

Why choose this principle:

The process segments feature formation into multiple steps: first forming a mandrel pattern at a larger pitch, then forming spacers on mandrel sidewalls, removing mandrels, and repeating the process to achieve sub-37.5 nm critical dimensions. This segmentation allows each step to operate within reliable photolithography limits while achieving smaller final dimensions

TRIZ inspiration library
17 Another dimension (Dimensionality change)
Try to solve problems with it

Principle concept:

If conventional photolithography techniques are used, then features can be formed with standard dimensions, but features with critical dimensions below 37.5 nm cannot be reliably formed due to optics limitations and radiation wavelength constraints

Why choose this principle:

The invention uses the vertical dimension by forming three-dimensional spacer structures on mandrel sidewalls. The spacer thickness, controlled by conformal deposition, defines the final feature dimension, transitioning from two-dimensional planar lithography to three-dimensional structure-based dimensioning

Application Domain

semiconductor devices sub-resolution features anti-spacer process

Data Source

Patent US20140370684A1 Methods for forming sub-resolution features in semiconductor devices
Publication Date: 18 Dec 2014 TRIZ 电器元件
FIG 01
US20140370684A1-D00000
FIG 02
US20140370684A1-D00001
FIG 03
US20140370684A1-D00002
Login to view Image

AI summary:

The anti-spacer process is employed, which involves chemically modifying the outer portions of photosensitive materials to make them soluble, forming filler materials between them, and removing these portions to create trenches and openings, allowing for the formation of features with smaller dimensions by extending holes into the substrate, thereby reducing the complexity and cost compared to conventional pitch multiplication techniques.

Abstract

Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of the second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.

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    anti-spacer process semiconductor devices sub-resolution features
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    Table of Contents
    • Sub-Resolution Feature Formation in Semiconductor Devices
      • Summary
      • TRIZ Analysis
      • Data Source
      • Accelerate from idea to impact
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