Thermal Expansion Solutions for Reliable Via Structures
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Summary
Problems
In semiconductor devices, through-silicon via (TSV) technology faces challenges due to thermal expansion mismatch between conductive materials and substrates, leading to protrusion and reliability issues during high-temperature processes, causing cracks and lifted layers.
Innovation solutions
A via structure is designed with a buffer pattern having a lower thermal expansion coefficient than the conductive pattern, which is formed on the inner wall and partially fills the via hole, accompanied by a second conductive pattern on top, ensuring the top surface remains coplanar with the substrate, thereby reducing thermal expansion and preventing protrusion.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a conductive material is used in the via hole for electrical connection, then the electrical connectivity is achieved, but the conductive material protrudes from the via hole due to thermal expansion mismatch during high temperature processes
Why choose this principle:
The patent introduces a buffer layer with specific material properties (lower thermal expansion coefficient) to modify the thermal expansion behavior of the via structure. This parameter change in the buffer layer compensates for the thermal expansion of the conductive material, preventing protrusion while maintaining electrical connectivity and structural integrity during high temperature processes.
Principle concept:
If the conductive material fills the via hole completely, then the electrical conductivity is maximized, but the thermal expansion causes protrusion and cracking of overlying layers
Why choose this principle:
The buffer layer acts as an intermediary between the conductive material and the surrounding substrate and overlying layers. It absorbs and compensates for the thermal expansion of the conductive material, preventing the transmission of expansion forces that would cause protrusion and cracking. This intermediary layer maintains the integrity of the entire via structure during thermal processing.
Application Domain
Data Source
AI summary:
A via structure is designed with a buffer pattern having a lower thermal expansion coefficient than the conductive pattern, which is formed on the inner wall and partially fills the via hole, accompanied by a second conductive pattern on top, ensuring the top surface remains coplanar with the substrate, thereby reducing thermal expansion and preventing protrusion.
Abstract
A via structure may include a first conductive pattern, a buffer pattern, and a second conductive pattern. The first conductive pattern may be on an inner wall of a first substrate and the inner wall may define a via hole passing at least partially through the first substrate. The buffer pattern may be on the first conductive pattern and the buffer pattern may partially fill the via hole. The second conductive pattern may be on a top surface of the buffer pattern in the via hole.