Reducing Transistor Variability with Gradual Strain-Inducing Cavities
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Summary
Problems
The fabrication of advanced integrated circuits faces challenges in maintaining high channel controllability and reducing variability in transistor performance due to non-uniformities in the deposition and etching processes during the formation of strained silicon/germanium alloy in CMOS technology, leading to increased variability and reduced production yield.
Innovation solutions
The use of two or more dedicated spacer elements to form gradually shaped cavities and strain-inducing semiconductor alloys, allowing for enhanced controllability and flexibility in defining the strain-inducing alloy configuration, thereby reducing process non-uniformities and variability, and enabling a high strain-inducing effect while maintaining uniformity and scalability.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a single etching process is used to form cavities for strain-inducing material, then the process is simple and fast, but the lateral offset and depth are non-uniform leading to high transistor variability
Why choose this principle:
The single etching process is segmented into multiple sequential etching processes, each forming a portion of the final cavity. The first etching process forms an initial cavity with a first lateral offset, and the second etching process forms an additional cavity portion with a second lateral offset. This segmentation allows each individual etching step to operate within optimal parameter ranges, achieving uniform lateral offsets that would be difficult to obtain in a single process step.
Principle concept:
If a single etching process is used to form cavities for strain-inducing material, then the process is simple and fast, but the lateral offset and depth are non-uniform leading to high transistor variability
Why choose this principle:
The first etching process performs a preliminary action by forming an initial cavity structure that serves as a foundation for the second etching process. This preliminary cavity formation establishes a controlled starting point with a first lateral offset, which then guides the subsequent second etching process to achieve the final desired cavity configuration with improved uniformity.
Application Domain
Data Source
AI summary:
The use of two or more dedicated spacer elements to form gradually shaped cavities and strain-inducing semiconductor alloys, allowing for enhanced controllability and flexibility in defining the strain-inducing alloy configuration, thereby reducing process non-uniformities and variability, and enabling a high strain-inducing effect while maintaining uniformity and scalability.
Abstract
In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.