Vertical Channel Transistor Design for Stable Semiconductor Performance
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Summary
Problems
In semiconductor devices, particularly dynamic random access memories (DRAMs), the reduction in transistor channel lengths leads to issues like the short channel effect, body floating, and threshold voltage variations due to hole charges, which are challenging to address in planar transistor structures as they scale down.
Innovation solutions
A semiconductor device and manufacturing method involving vertical channel transistors with pillar patterns, word lines, and body contacts are used, where a bias is applied through silicon lines and metal contacts to prevent body floating by draining holes, and the use of conductive materials like titanium nitride and tungsten for word lines and body contacts.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the channel length of transistors is reduced to increase integration density, then the integration density is improved, but short channel effects such as drain induced barrier lowering, hot carrier effect, and punch-through occur
Why choose this principle:
The patent transitions from a planar transistor structure to a vertical channel transistor structure. The channel is formed vertically through the substrate rather than horizontally on the surface, utilizing the third dimension (depth) to achieve shorter channel lengths while maintaining better control over short channel effects. This dimensional change allows higher integration density without sacrificing transistor performance stability.
Principle concept:
If the channel length of transistors is reduced to increase integration density, then the integration density is improved, but short channel effects such as drain induced barrier lowering, hot carrier effect, and punch-through occur
Why choose this principle:
The patent divides the channel region into multiple segments by forming isolated pillar patterns with vertical channels. Each pillar represents a segmented channel structure that can be independently controlled. This segmentation allows for better electrostatic control and reduces the impact of short channel effects while maintaining compact device area for high integration density.
Application Domain
Data Source
AI summary:
A semiconductor device and manufacturing method involving vertical channel transistors with pillar patterns, word lines, and body contacts are used, where a bias is applied through silicon lines and metal contacts to prevent body floating by draining holes, and the use of conductive materials like titanium nitride and tungsten for word lines and body contacts.
Abstract
A semiconductor device includes a first buried bit line ( 120 a ) provided between lower and upper substrates ( 100 b, 100 a ), first and second pillar patterns ( 105 a, 105 b ) extending from the upper substrate ( 100 a ) and coupled to the first buried bit line ( 120 a ) through first and second gate patterns ( 140 a ), respectively. A first body contact pattern ( 160 a ) coupled to the first and/or the second pillar patterns ( 105 a, 105 b ) through the upper substrate ( 100 a ) prevents the first and the second pillar patterns from floating.