Wafer Fill Patterns for Improved Etching Precision
Here’s PatSnap Eureka !
Summary
Problems
In semiconductor device processing, particularly in multiple-step patterning processes like double etch double exposure, controlling the intermediate etch patterning is challenging due to process sensitivities, especially when the gate width is narrow, leading to insufficient gate oxide as an optical endpoint for timed etching.
Innovation solutions
The method involves forming a hardmask layer with fill shapes and cut-away holes in the inactive region to enhance optical endpoint detection and control the etching process, allowing for accurate pattern transfer and reflectivity adjustments.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a timed etch is used for intermediate pattern transfer, then the etching process can be simplified, but the process control becomes difficult due to insufficient gate oxide as optical endpoint
Why choose this principle:
The patent applies preliminary action by forming additional gate oxide layers in advance before the etching process. Specifically, a first gate oxide layer is formed before the first resist pattern, and a second gate oxide layer is formed between the first and second resist patterns. These pre-formed oxide layers ensure sufficient optical endpoint is available when needed for the timed etch process, resolving the contradiction between process simplicity and control precision.
Principle concept:
If the gate width is reduced to increase device density, then more devices can be packed, but there is not enough gate oxide to serve as an effective optical endpoint
Why choose this principle:
The patent resolves this contradiction by adding a temporal dimension to the oxide layer structure. Instead of relying solely on the lateral dimension (gate width), the solution introduces oxide layers formed at different time points in the process sequence. The first gate oxide layer is formed before the first resist pattern, and the second gate oxide layer is formed between the two resist patterns, creating sufficient optical endpoint in the vertical/time dimension even when gate width is reduced for higher density.
Application Domain
Data Source
AI summary:
The method involves forming a hardmask layer with fill shapes and cut-away holes in the inactive region to enhance optical endpoint detection and control the etching process, allowing for accurate pattern transfer and reflectivity adjustments.
Abstract
A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.