Cobalt Semiconductor Material: Advanced Applications In Contact Metallization And Silicide Formation For VLSI Devices

Chemical Composition And Purity Requirements For Cobalt Semiconductor Material

Cobalt semiconductor material demands exceptionally high purity levels to prevent device malfunction and performance degradation in VLSI and ULSI applications 5. Crude cobalt traded globally typically exhibits purity levels of 98–99.8%, containing detrimental impurities such as transition metals (nickel, iron, chromium), gas elements (oxygen, nitrogen, sulfur), and trace radioactive elements (uranium, thorium) 8. Copper impurities are particularly problematic due to their high diffusion rate in silicon, potentially causing short circuits, while radioactive elements induce soft errors in memory devices 5. Alkaline and alkaline-earth metals degrade dielectric properties and gate oxide integrity 8.

Purification Methodologies And Industrial Challenges

Traditional purification approaches include solvent extraction, ion exchange, electrolytic refining, and hydrogen gas treatment for gas element removal 5. However, solvent extraction suffers from difficult control of extraction/reverse-extraction equilibria in industrial-scale processes 8. Ion exchange effectively removes most metallic impurities but exhibits negligible copper removal efficiency 5. Electrolytic refining requires stringent pH control and similarly struggles with nickel and copper separation 8. Floating zone melting refining, while effective for certain metals, demonstrates minimal purification effects on cobalt (V.G. Glebovsky et al., Materials Letters 36, 1998, pp.308-314) 5. Advanced purification protocols combining multiple techniques are essential to achieve the <5 ppm total impurity levels required for semiconductor-grade cobalt targets used in physical vapor deposition (PVD) systems 8.

Target Material Specifications For Semiconductor Processing

High-purity cobalt targets for sputtering applications must meet stringent compositional specifications: copper content <0.5 ppm, nickel <1 ppm, iron <1 ppm, oxygen <10 ppm, and radioactive elements below detection limits (<0.01 ppb for uranium and thorium) 5. Grain structure and crystallographic texture of the target material significantly influence deposition uniformity and film stress. Targets with <111> preferred orientation yield cobalt films with lower resistivity (5–6 μΩ·cm at 25°C) compared to randomly oriented polycrystalline deposits 8. For atomic layer deposition (ALD) applications, organometallic cobalt precursors such as cobalt tricarbonyl nitrosyl [Co(CO)₃NO] or cobaltocene derivatives require >99.999% purity and controlled ligand chemistry to ensure clean decomposition without carbon or oxygen incorporation 2.

Deposition Techniques And Film Formation Mechanisms For Cobalt Semiconductor Material

Physical Vapor Deposition: Sputtering Process Optimization

Sputtering remains the dominant method for depositing cobalt semiconductor material in production environments due to excellent thickness control, uniformity, and scalability 9. Optimized sputtering conditions for cobalt film deposition include: argon atmosphere at 0.1–1 mTorr, substrate temperature maintained at 200–370°C, RF bias power of 200–600 W applied to the silicon substrate, and deposition rates of 1.92–3.37 nm/s with concurrent resputtering rates of 0.10–0.68 nm/s 16. These parameters yield flat, conformal cobalt films with minimal surface roughness (<0.5 nm RMS), critical for subsequent silicidation reactions 16. Lower chamber pressures (<0.5 mTorr) reduce gas-phase scattering, improving step coverage in high-aspect-ratio features (>10:1) 6. Substrate heating during deposition enhances adatom mobility, promoting dense film microstructure and reducing void formation at grain boundaries 16.

Atomic Layer Deposition: Nucleation And Surface Chemistry

Atomic layer deposition (ALD) of cobalt semiconductor material enables conformal coating of complex 3D structures with sub-nanometer thickness control, essential for FinFET and gate-all-around (GAA) transistor architectures 2. A critical challenge in cobalt ALD is achieving nucleation on bare silicon without an interfacial oxide layer, which increases contact resistance 14. A novel nucleation method involves pre-treating the atomically clean silicon surface with tantalum nitride or titanium nitride precursors (e.g., PDMAT or TDMAT) at 250–350°C, creating reactive surface sites for subsequent cobalt precursor adsorption 14. Following purge cycles, organometallic cobalt precursors such as Co(EtCp)₂ or Co(DMAP)₂ are introduced at 200–300°C, forming a cobalt nucleation layer 0.5–1.5 nm thick 2. Hydrogen-containing gas treatment (H₂ or NH₃ plasma) at 300–400°C removes residual ligands and reduces cobalt oxide, yielding metallic cobalt films with resistivity <10 μΩ·cm and <2 at.% impurity content 2. This approach enables direct cobalt-on-silicon contacts with interface resistances <1×10⁻⁸ Ω·cm², significantly lower than conventional TiN-barrier-mediated contacts 14.

Chemical Vapor Deposition And Precursor Design

Thermal CVD and plasma-enhanced CVD (PECVD) of cobalt semiconductor material utilize volatile organometallic precursors that decompose on heated substrates (300–450°C for thermal CVD, 200–350°C for PECVD) 10. Precursor design focuses on compounds with sufficient vapor pressure (>0.1 Torr at 80–120°C), clean decomposition pathways, and atmospheric stability 10. A representative precursor class comprises cobalt complexes with halogen-substituted ligands, such as Co(hfac)₂ (hexafluoroacetylacetonate), which exhibit enhanced volatility and reduced carbon incorporation compared to unsubstituted analogs 10. Deposition rates of 5–20 nm/min are achievable with precursor flow rates of 50–200 sccm and chamber pressures of 1–10 Torr 10. Post-deposition annealing in forming gas (5% H₂ in N₂) at 400–500°C for 30–60 minutes reduces oxygen and carbon impurities to <1 at.%, improving film conductivity and silicidation kinetics 10.

Cobalt Silicide Formation: Phase Evolution And Electrical Properties

Silicidation Reaction Mechanisms And Phase Sequence

Cobalt silicide formation proceeds through a well-defined phase sequence upon thermal annealing of cobalt films on silicon substrates 3. Initial annealing at 400–550°C induces solid-state reaction between cobalt and silicon, forming metastable Co₂Si phase with orthorhombic crystal structure 7. The reaction stoichiometry follows: 2Co + Si → Co₂Si 7. Continued annealing at 550–700°C transforms Co₂Si to the thermodynamically stable CoSi phase (cubic B20 structure) via the reaction: Co₂Si + Si → 2CoSi 3. Further heating above 700°C yields CoSi₂ (cubic CaF₂ structure), the lowest-resistivity phase (15–20 μΩ·cm), through: CoSi + Si → CoSi₂ 7. However, CoSi₂ formation consumes excessive silicon, making it unsuitable for ultra-shallow junctions (<50 nm) 3. Therefore, modern processes target CoSi phase formation, which exhibits resistivity of 50–70 μΩ·cm and minimal silicon consumption (Si:Co atomic ratio of 1:1) 7.

Alloying Strategies For Enhanced Silicide Performance

Incorporating alloying elements into cobalt semiconductor material significantly improves silicide properties and process robustness 3. Co-Ti alloy films (5–15 at.% Ti) deposited via co-sputtering exhibit superior thermal stability and reduced agglomeration compared to pure cobalt silicides 3. The titanium forms a TiN diffusion barrier at the silicide/dielectric interface during annealing in nitrogen ambient, preventing cobalt diffusion into interlayer dielectrics 3. This approach yields contact resistances <2×10⁻⁸ Ω·cm² for 0.13 μm technology nodes with minimal line-width dependence 3. Nickel or iron additions (2–10 at.%) to cobalt silicide films inhibit cobalt atom diffusion during high-temperature processing (>800°C), preventing junction spiking and maintaining low sheet resistance (<10 Ω/sq for 20 nm films) even after prolonged thermal exposure 4. The mechanism involves substitutional incorporation of Ni or Fe atoms into the CoSi lattice, reducing cobalt vacancy concentration and suppressing grain boundary diffusion 12.

Process Integration And Selective Silicidation

Self-aligned silicide (salicide) processes integrate cobalt silicide formation with gate and source/drain contact metallization in a single thermal budget 9. Following gate patterning and spacer formation, cobalt films (10–30 nm) are blanket-deposited via sputtering at substrate temperatures of 250–350°C 15. A capping layer of titanium nitride (10–14 nm) is deposited immediately after cobalt to prevent oxidation and control silicidation kinetics 15. Rapid thermal annealing (RTA) at 450–550°C for 30–60 seconds in nitrogen ambient initiates selective silicide formation on exposed silicon regions (gate polysilicon and source/drain), while cobalt on dielectric spacers remains unreacted 15. Wet etching in H₂SO₄:H₂O₂ (4:1) solution at 60–80°C selectively removes unreacted cobalt and TiN, leaving CoSi on active regions 15. A second RTA at 700–800°C for 30 seconds converts CoSi to lower-resistivity CoSi₂ if required, though this step is often omitted for sub-50 nm gates to minimize silicon consumption 15. This process achieves gate sheet resistance <5 Ω/sq and contact resistance <1×10⁻⁸ Ω·cm² for 45 nm technology nodes 15.

Advanced Applications Of Cobalt Semiconductor Material In Nanoscale Devices

Contact Plugs And Via Metallization For Sub-10 nm Nodes

Cobalt semiconductor material has emerged as the preferred contact plug metal for 10 nm, 7 nm, and 5 nm logic technology nodes, displacing tungsten due to superior gap-fill capability and lower resistivity in high-aspect-ratio structures 6. Cobalt contact plugs are formed by ALD or CVD deposition into patterned interlayer dielectric openings with aspect ratios exceeding 10:1 (height:width) 6. A thin metal liner (TiN, TaN, or Co-W alloy, 1–3 nm) is deposited prior to cobalt fill to improve adhesion and prevent copper diffusion from overlying interconnects 6. Void-free cobalt fill is achieved through optimized deposition conditions: substrate temperature 300–400°C, precursor pulse time 0.5–2 seconds, and hydrogen co-reactant flow of 50–200 sccm 6. Post-deposition annealing at 400–500°C for 30–60 minutes in forming gas increases cobalt grain size from 10–20 nm to 50–100 nm, reducing resistivity from 8–10 μΩ·cm to 6–7 μΩ·cm through decreased grain boundary scattering 6. A stress control layer (SiN or SiCN, 5–10 nm) deposited atop the cobalt prevents extrusion during subsequent thermal processing 6. This integration scheme achieves contact resistances <5×10⁻⁹ Ω·cm² for 7 nm node devices, enabling continued CMOS scaling 6.

Cobalt-Tungsten Hybrid Metallization Schemes

Hybrid metallization combining cobalt semiconductor material for contact plugs and tungsten for vias optimizes electrical performance and process complexity 13. Cobalt is selectively deposited in contact-level openings (aspect ratio 8:1 to 15:1) using ALD, providing low-resistance connection to source/drain regions 13. Following cobalt deposition and chemical-mechanical polishing (CMP) to planarize the surface, a hydrogen soak treatment at 350–450°C for 5–15 minutes in 5% H₂/N₂ ambient reduces surface cobalt oxide and improves tungsten nucleation 13. Tungsten is then deposited via CVD using WF₆ and H₂ precursors at 350–450°C, filling via-level openings (aspect ratio 3:1 to 6:1) that connect to the underlying cobalt contacts 13. This approach leverages cobalt's superior gap-fill for high-aspect-ratio contacts while utilizing tungsten's mature process technology and lower cost for larger-diameter vias 13. Electrical characterization demonstrates 15–25% reduction in via chain resistance compared to all-tungsten metallization, attributed to the lower resistivity cobalt contact interface 13.

Cobalt Alloy Barrier Layers For Copper Interconnects

Cobalt alloy barrier layers address the dual challenges of copper diffusion prevention and resistance reduction in advanced interconnect structures 11. Traditional TaN/Ta barrier stacks consume 20–30% of interconnect cross-sectional area in sub-20 nm pitch lines, significantly increasing line resistance 11. Cobalt-tungsten-phosphorus (Co-W-P) and cobalt-molybdenum (Co-Mo) alloys deposited by electroless plating or ALD provide effective copper diffusion barriers at reduced thickness (2–5 nm) 11. The alloy composition is optimized to achieve amorphous or nanocrystalline microstructure, eliminating fast diffusion paths along grain boundaries 11. For example, Co-W-P alloys with 5–15 at.% W and 2–8 at.% P exhibit copper diffusion coefficients <1×10⁻¹⁶ cm²/s at 400°C, three orders of magnitude lower than pure cobalt 11. These barriers maintain integrity after 1000 hours at 400°C in copper/barrier/dielectric stacks, meeting reliability requirements for 7 nm and 5 nm nodes 11. Integration involves depositing the cobalt alloy barrier, followed by copper seed layer (PVD or ALD, 3–10 nm) and electroplated copper fill 11. This approach reduces interconnect resistance by 10–20% compared to TaN/Ta barriers while maintaining equivalent reliability 11.

Cobalt In FinFET And Gate-All-Around Transistor Architectures

Three-dimensional transistor architectures such as FinFETs and gate-all-around (GAA) nanowire/nanosheet FETs impose stringent conformality and thickness control requirements on contact metallization 11. Cobalt semiconductor material deposited by ALD enables conformal coating of fin sidewalls and nanowire surfaces with thickness uniformity >95% 11. For FinFET source/drain contacts, cobalt is selectively deposited on epitaxially grown SiGe or Si:P stressor regions following spacer formation and silicidation 11. ALD cobalt deposition at 275–325°C using Co(EtCp)₂ precursor and H₂ plasma co-reactant yields 5–15 nm conformal films with step coverage >98% on fin structures with 5:1 aspect ratio 11. Subsequent annealing at 400°C converts the cobalt to CoSi at the silicon interface, forming a low-resistance contact (ρc < 5×10⁻⁹ Ω·cm²) while maintaining cobalt metal on the upper contact region 11. For GAA transistors, cobalt gate metal deposition via ALD enables work function tuning through controlled cobalt thickness (3–8 nm) and post-deposition nitridation treatments 11. This integration reduces parasitic source/drain resistance by 30–40% compared to tungsten contacts, directly improving transistor drive current and circuit speed 11.

Capping Layers And Interface Engineering For Cobalt Semiconductor Material

Titanium Nit