Fan-Out Packaging Glass Core Substrate: Advanced Integration Technology For High-Density Interconnection

Fundamental Material Properties And Structural Characteristics Of Fan-Out Packaging Glass Core Substrate

Fan-out packaging glass core substrates leverage the intrinsic advantages of glass materials to overcome limitations inherent in conventional organic and silicon-based substrates. The glass core typically consists of fusion-drawn or chemically strengthened glass with precisely controlled coefficient of thermal expansion (CTE) values. Research demonstrates that laminated glass structures comprising a core layer and cladding layers can achieve CTE values ranging from 3.0 to 9.0 ppm/°C through compositional tuning and thickness ratio optimization 9. This CTE tunability is critical for minimizing in-process warpage during fan-out packaging, where thermal cycling between room temperature and processing temperatures (typically 150–260°C) can induce significant substrate deformation.

The mechanical properties of glass core substrates include:

• Elastic modulus: 70–90 GPa, providing superior dimensional stability compared to organic substrates (3–25 GPa) 3
• Surface roughness: Ra < 0.5 nm for fusion-drawn glass, enabling ultra-fine lithography for RDL formation with line/space dimensions down to 2/2 μm 1
• Dielectric constant: εr = 5.5–7.0 at 1 GHz, with dissipation factor (tan δ) < 0.01, significantly lower than epoxy-based molding compounds (εr = 3.5–4.5, tan δ = 0.02–0.03) 38
• Thermal conductivity: 1.0–1.4 W/m·K, adequate for moderate power dissipation applications when combined with thermal interface materials 6

Glass core substrates for fan-out packaging are typically fabricated in thicknesses ranging from 100 μm to 500 μm, with through-glass vias (TGVs) formed by laser drilling, wet etching, or photosensitive glass processes 13. The via diameter ranges from 20 μm to 100 μm with aspect ratios up to 5:1, filled with electroplated copper to provide vertical electrical interconnection 3. A critical innovation involves the use of differential etch-rate glass laminates, where a high-etch-rate cladding layer (e.g., borosilicate composition) is fused to a low-etch-rate core layer (e.g., aluminosilicate composition), enabling selective cavity formation for die embedding without compromising the structural integrity of the core 1.

The glass substrate's impermeability to moisture (water absorption < 0.01% at 85°C/85% RH for 168 hours) and chemical inertness provide long-term reliability advantages over organic substrates, particularly in harsh environmental conditions 312. Additionally, the optical transparency of glass substrates facilitates alignment and inspection processes during manufacturing, reducing defect rates in high-volume production 1.

Precursors, Synthesis Routes, And Manufacturing Processes For Glass Core Substrates In Fan-Out Packaging

The production of glass core substrates for fan-out packaging involves multiple process steps, each requiring precise control to achieve the desired material properties and dimensional tolerances. The primary manufacturing routes include:

Fusion Draw Process For Laminated Glass Substrates

The fusion draw process, pioneered for display glass manufacturing, has been adapted for producing laminated glass substrates with controlled CTE profiles 9. In this process, molten glass compositions for the core and cladding layers are simultaneously fed into a fusion draw apparatus, where they flow over a refractory trough and fuse together while being drawn downward. The resulting laminate exhibits a graded interface with strong chemical bonding between layers, eliminating delamination risks during subsequent processing 9.

Key process parameters include:

• Core glass composition: Aluminosilicate or boroaluminosilicate with SiO₂ (55–70 wt%), Al₂O₃ (10–20 wt%), B₂O₃ (0–15 wt%), and alkaline earth oxides (5–15 wt%) to achieve CTE of 3.0–5.0 ppm/°C 9
• Cladding glass composition: Modified borosilicate with higher alkali content to achieve CTE of 5.0–9.0 ppm/°C and etch rate 5–20× higher than core glass in HF-based etchants 19
• Draw temperature: 1100–1300°C, with cooling rate controlled to minimize residual stress (< 5 MPa) 9
• Thickness control: ±5 μm tolerance across 300 mm diameter substrates, achieved through real-time optical monitoring and draw speed adjustment 9

The fusion draw process enables production of glass substrates with total thickness variation (TTV) < 2 μm and warp < 50 μm for 300 mm diameter substrates, critical for subsequent lithography and thin-film deposition processes 19.

Through-Glass Via (TGV) Formation And Metallization

TGV formation is a critical step in creating vertical electrical interconnections through the glass core substrate. Multiple techniques are employed depending on via diameter, aspect ratio, and throughput requirements:

Laser drilling: Ultraviolet (UV) or infrared (IR) picosecond or femtosecond lasers ablate glass material to form vias with diameters of 20–100 μm. Process parameters include laser fluence of 2–10 J/cm², pulse repetition rate of 100–500 kHz, and multiple passes (5–20) to achieve the desired depth 3. Post-drilling wet etching in dilute HF (5–10% concentration, 5–15 minutes at 25°C) smooths via sidewalls and removes debris, reducing sidewall roughness from Ra = 500 nm to Ra < 100 nm 3.

Wet chemical etching: For high-etch-rate cladding layers, photolithography-defined cavities are etched using HF-based solutions (10–20% HF, 30–120 minutes at 25–40°C) to create cavities with depths of 50–300 μm and lateral dimensions of 500 μm to 5 mm for die embedding 1. The etch selectivity between cladding and core layers (typically 10:1 to 20:1) enables precise depth control, with the core layer acting as an etch stop 1.

Via metallization: Following via formation, a barrier/seed layer (Ti/Cu or Ta/Cu, 50–200 nm total thickness) is deposited by sputtering or atomic layer deposition (ALD) to ensure conformal coverage of via sidewalls 3. Electroplating of copper (99.9% purity) fills the vias, with plating current density of 1–5 A/dm², bath temperature of 25–35°C, and plating time of 30–120 minutes depending on via depth 3. Chemical-mechanical polishing (CMP) planarizes the substrate surface, removing excess copper and achieving surface roughness Ra < 10 nm 3.

Build-Up Layer Fabrication And Redistribution Layer (RDL) Formation

Following TGV formation and metallization, build-up layers comprising dielectric films and RDL metal traces are fabricated on both sides of the glass core substrate. The build-up process typically involves:

• Dielectric layer deposition: Spin-coating or lamination of photosensitive polyimide (PI) or polybenzoxazole (PBO) films with thickness of 2–10 μm per layer, followed by UV exposure (200–500 mJ/cm²), development, and thermal curing (300–350°C, 1–2 hours in nitrogen atmosphere) 357
• RDL patterning: Photolithography using i-line (365 nm) or DUV (248 nm) exposure systems to define RDL patterns with line/space dimensions of 2/2 μm to 10/10 μm, followed by electroplating of copper (3–15 μm thickness) and wet etching of the seed layer 5714
• Via opening: Laser ablation or plasma etching (O₂/CF₄ chemistry, 200–500 W power, 5–20 minutes) to open vias in the dielectric layer, exposing underlying metal pads for vertical interconnection 57

Multiple build-up layers (typically 2–6 layers per side) are sequentially fabricated to achieve the required routing density and I/O count, with total build-up thickness ranging from 20 μm to 100 μm per side 3514.

Die Embedding, Encapsulation, And Fan-Out Structure Formation On Glass Core Substrates

A distinguishing feature of fan-out packaging with glass core substrates is the ability to embed dies within cavities etched into the glass substrate, providing superior dimensional stability and enabling ultra-thin package profiles. The die embedding and encapsulation process involves:

Cavity Formation And Die Placement

Cavities for die embedding are formed in the high-etch-rate cladding layer of the glass substrate using wet chemical etching, as described previously 1. The cavity depth is precisely controlled to match the die thickness (typically 50–200 μm for thinned dies), with an additional clearance of 5–20 μm to accommodate die placement tolerances 1. Dies are placed into the cavities using high-precision pick-and-place equipment with placement accuracy of ±5 μm, and temporarily bonded using thermoplastic adhesive films or UV-curable adhesives 157.

For die-up configurations, where the active surface of the die faces away from the glass substrate, the die backside is bonded to the cavity bottom, and wire bonding or flip-chip interconnections are subsequently formed to connect die pads to the RDL 15. For die-down configurations, the die active surface faces the glass substrate, and hybrid bonding or micro-bump interconnections provide electrical connection to underlying metal pads 716.

Encapsulation Materials And Processes

Following die placement, encapsulation materials are applied to fill the gaps around the dies and provide mechanical protection. Two primary encapsulation approaches are employed:

Compression molding with epoxy molding compound (EMC): Traditional thermosetting EMC materials (epoxy resin with silica filler, 70–90 wt% filler loading) are compression-molded at 175–180°C under 5–10 MPa pressure for 90–180 seconds 2613. The EMC flows around the dies and fills the cavities, followed by post-mold curing at 175°C for 2–4 hours 13. However, EMC materials exhibit relatively high CTE (12–18 ppm/°C) and dissipation factor (tan δ = 0.02–0.03 at 1 GHz), limiting their suitability for high-frequency applications 8.

Thermoplastic encapsulation: To address the limitations of thermosetting EMC, thermoplastic materials such as liquid crystal polymer (LCP) or polyetherimide (PEI) films are laminated onto the glass substrate at 250–300°C under 1–3 MPa pressure 8. Thermoplastic materials offer lower dissipation factor (tan δ < 0.005 at 1 GHz) and can be reworked or recycled, but require higher processing temperatures 8. Via holes in the glass substrate enable the thermoplastic material on both sides of the substrate to interconnect, enhancing mechanical stability 8.

Liquid encapsulants: For applications requiring void-free encapsulation, liquid epoxy or silicone-based encapsulants are dispensed or printed onto the substrate, followed by vacuum degassing and thermal curing at 120–150°C for 1–2 hours 17. Liquid encapsulants provide excellent gap-filling capability for fine-pitch die arrays and enable selective encapsulation of specific regions 1.

Warpage Control And CTE Matching Strategies

Warpage during fan-out packaging processes is a critical challenge, particularly during high-temperature steps such as RDL formation, encapsulation, and solder reflow. Glass core substrates with tunable CTE enable precise matching to the effective CTE of the reconstituted wafer or panel, minimizing warpage 9. Research demonstrates that by selectively removing a portion of the high-CTE cladding layer after die embedding and RDL formation, the effective CTE of the glass substrate can be adjusted in increments of 0.1 ppm/°C, enabling fine-tuning to achieve warp < 100 μm for 300 mm diameter substrates throughout the entire process 9.

Additional warpage control strategies include:

• Symmetric build-up layer design: Balancing the number and thickness of dielectric and metal layers on both sides of the glass core to minimize bending moments 39
• Low-temperature processing: Using low-cure-temperature dielectric materials (< 200°C) and solder alloys (e.g., SnBi with melting point of 138°C) to reduce thermal stress 57
• Mechanical reinforcement: Temporarily bonding the glass substrate to a rigid carrier plate during processing to constrain warpage, followed by carrier removal after completion of high-temperature steps 911

Electrical Performance, Signal Integrity, And High-Frequency Characteristics Of Glass Core Substrates

Glass core substrates offer significant advantages in electrical performance compared to organic substrates, particularly for high-frequency and high-speed digital applications. Key electrical characteristics include:

Dielectric Properties And Loss Tangent

The dielectric constant (εr) of glass core substrates ranges from 5.5 to 7.0 at frequencies from 1 GHz to 10 GHz, with minimal frequency dependence 38. This is higher than organic substrates (εr = 3.5–4.5) but lower than silicon (εr = 11.9), providing a balanced trade-off between signal propagation speed and capacitive loading 3. The dissipation factor (tan δ) of glass is typically < 0.01 at 1 GHz, significantly lower than epoxy-based materials (tan δ = 0.02–0.03), resulting in reduced signal attenuation and lower insertion loss for high-frequency transmission lines 8.

For a 50 Ω microstrip transmission line on a glass core substrate (εr = 6.5, tan δ = 0.008) with 10 μm thick copper traces, the insertion loss at 10 GHz is approximately 0.8 dB/cm, compared to 1.2 dB/cm for an equivalent organic substrate 8. This 33% reduction in loss is critical for maintaining signal integrity in high-speed serial links operating at data rates > 25 Gbps 8.

Impedance Control And Crosstalk Reduction

The dimensional stability and low surface roughness of glass core substrates enable precise control of transmission line impedance, with tolerances of ±5% achievable for 50 Ω differential pairs 3. The low dielectric loss and high resistivity (> 10¹⁴ Ω·cm) of glass minimize substrate-induced crosstalk, with near-end crosstalk (NEXT) < -40 dB and far-end crosstalk (FEXT) < -50 dB for adjacent 100 μm pitch differential pairs at 10 GHz 3.

Power Delivery Network (PDN) Performance

Glass core substrates with embedded decoupling capacitors and low-inductance TGVs provide superior PDN performance compared to organic substrates. The low-inductance TGVs (typically 10–50 pH per via, compared to 100–200 pH for through-holes in organic substrates) enable efficient power delivery to high-current dies, reducing voltage droop and improving transient response 3. Embedded thin-film capacitors (e.g., SiO₂/Si₃N₄ multilayers with capacitance density of 100–500 nF/cm²) can be integrated into the glass substrate to provide localized decoupling, further enhancing PDN performance 3.

Applications Of Fan-Out Packaging Glass Core Substrate In Advanced Microelectronic Systems

Fan-out packaging glass core substrates are being adopted across multiple application domains, driven by their superior material properties and enabling capabilities for heterogeneous integration.

Mobile And Consumer Electronics — Application Processors And Baseband