Fine Line Redistribution Glass Core Substrate: Advanced Manufacturing Technologies And Performance Optimization For High-Density Interconnect Applications

Structural Architecture And Design Principles Of Fine Line Redistribution Glass Core Substrates

The fundamental architecture of fine line redistribution glass core substrates integrates multiple functional layers to achieve electrical connectivity, mechanical robustness, and thermal management. A typical structure comprises a glass core layer (thickness 50–500 μm) sandwiched between organic buildup layers, with through-glass vias (TGVs) or conductive micro vias providing vertical electrical pathways 1,2,5. The glass core itself may consist of single-layer or multi-layer laminated glass structures bonded with adhesive interlayers 7,14. For instance, a three-layer glass core substrate includes a first glass layer, a second glass layer disposed on the first, and bonding layers (e.g., epoxy-based or siloxane-based adhesives with glass transition temperature Tg >200°C) between them, with conductive connectors penetrating all layers to establish vertical conductive paths 7.

Recent innovations emphasize edge coating and profile control to mitigate stress concentration and warpage. Patent 1 discloses an apparatus where the glass core edge is offset from the edges of overlying and underlying organic dielectric substrates, with a conformal coating layer (typically polyimide or benzocyclobutene with thickness 5–20 μm) applied to the perimeter, ensuring the outer sidewall is substantially parallel to the glass edge. This design reduces edge delamination risk and improves mechanical reliability during thermal cycling (−55°C to 125°C, 1000 cycles) 1. Similarly, patent 2 describes a frame structure surrounding the glass core perimeter, providing additional mechanical support and preventing crack propagation from edge defects 2.

The integration of fine redistribution segments with coarse redistribution structures is critical for large-format substrates. Patent 10 presents a manufacturing method where fine redistribution segments (line width/space 2/2 μm, dielectric layer thickness 2–5 μm) are formed on a temporary carrier, segmented by trenches, and then coupled to a coarse redistribution structure (line width/space 10/10 μm, dielectric layer thickness 10–30 μm) via conductive connectors (copper pillars with diameter 30–100 μm, height 50–200 μm) 10. This hierarchical architecture enables fine-pitch chip connections on the top surface while maintaining cost-effective coarse routing in the core and bottom layers, addressing the challenge of manufacturing large substrates (>600 mm × 600 mm) with fine-line capability 10.

Material Properties And Performance Characteristics Of Glass Core Substrates

Glass core substrates exhibit superior material properties compared to traditional organic cores (e.g., FR-4, bismaleimide-triazine resin). Key performance parameters include:

• Dimensional Stability: Glass cores demonstrate ultra-low CTE (3.2–8.5 ppm/°C for borosilicate glass, 0.5–3.0 ppm/°C for fused silica) closely matching silicon (2.6 ppm/°C), minimizing thermomechanical stress during die attach and reflow processes (peak temperature 260°C) 3,9. This CTE matching reduces warpage to <50 μm for 300 mm × 300 mm substrates, compared to >200 μm for organic cores 9.

• Surface Flatness: Glass surfaces achieve roughness Ra <0.5 nm over 1 mm² scan areas, enabling photolithographic patterning of redistribution layers with line width down to 0.8 μm and positional accuracy ±0.5 μm 3,19. This flatness is critical for fine-line manufacturing, as surface irregularities >10 nm can cause photoresist thickness variation and pattern defects 19.

• Dielectric Properties: Borosilicate glass exhibits dielectric constant εr = 4.6–5.5 at 1 GHz and dissipation factor tan δ <0.005, providing low signal loss for high-frequency applications (>10 GHz) 11. Fused silica offers even lower εr = 3.8 and tan δ <0.001, suitable for millimeter-wave and 5G applications 11.

• Mechanical Strength: Glass cores have flexural strength 50–150 MPa (depending on composition and surface treatment) and Young's modulus 60–90 GPa, providing rigidity to prevent substrate bending during assembly 13,20. However, glass is brittle with fracture toughness KIC ~0.7–0.8 MPa·m^(1/2), necessitating careful stress management 20.

• Thermal Stability: Glass cores withstand processing temperatures up to 450°C without degradation, enabling high-temperature curing of polyimide dielectrics (cure temperature 350–400°C) and annealing of copper redistribution layers 9,11. Thermogravimetric analysis (TGA) shows <0.1% weight loss up to 500°C for borosilicate glass 9.

Patent 9 addresses the challenge of stress-induced cracking by introducing a dielectric buffer layer (thickness 0.5–5 μm, material: silicon dioxide, silicon nitride, or polyimide) between the glass core and conductive vias/pads 9. This buffer layer accommodates CTE mismatch between copper (CTE ~17 ppm/°C) and glass, reducing interfacial stress by 40–60% and preventing micro-crack formation during thermal cycling 9. Finite element analysis (FEA) simulations demonstrate that buffer layers reduce maximum principal stress at the glass-copper interface from 180 MPa to 70 MPa 9.

Manufacturing Processes And Technological Innovations For Fine Line Redistribution Glass Core Substrates

Through-Glass Via (TGV) Formation And Conductive Micro Via Arrays

Traditional TGV fabrication involves laser drilling (wavelength 355 nm or 1064 nm, pulse duration 10–100 ns, fluence 5–20 J/cm²) followed by wet chemical etching (hydrofluoric acid-based solutions, etch rate 1–10 μm/min) to achieve via diameters 20–100 μm and aspect ratios 1:1 to 5:1 3,18. However, this two-step process is costly, requires hazardous chemicals, and necessitates surface roughening (Ra 0.5–2 μm) to ensure copper adhesion, which is detrimental to fine-line RDL fabrication 3.

Patent 3 proposes an innovative approach using conductive micro via arrays to replace conventional TGVs 3. Each conductive region comprises a plurality of micro vias with diameters 2–10 μm, formed by laser ablation (femtosecond laser, wavelength 515 nm, pulse duration <500 fs, repetition rate 100–500 kHz) or photolithography combined with deep reactive ion etching (DRIE, etch rate 0.5–2 μm/min, selectivity >50:1) 3. The micro vias are filled with copper by electroplating (current density 1–5 A/dm², plating rate 2–10 μm/h, bath composition: CuSO₄ 200 g/L, H₂SO₄ 50 g/L, additives for superfilling) 3. This approach offers several advantages:

1. Reduced Manufacturing Cost: Eliminates the need for wet etching and specialty chemicals, reducing process steps by 30–40% 3.
2. Improved Surface Quality: Avoids aggressive roughening, maintaining glass surface Ra <1 nm, which is conducive to fine-line patterning (line width <2 μm) 3.
3. Enhanced Mechanical Strength: Distributes stress over multiple small vias rather than concentrating it around large TGVs, reducing crack initiation probability by 50–70% 3.
4. Higher Aspect Ratio Capability: Micro vias with aspect ratios up to 10:1 can be reliably filled using pulse-reverse electroplating techniques 3.

Patent 18 addresses crack formation during TGV drilling by intentionally creating controlled cracks at the via inner wall and filling them with conductive material 18. This method converts potential failure sites into reinforced structures, improving via reliability under thermal and mechanical stress 18.

Fine Line Redistribution Layer (RDL) Fabrication

Fine line RDL manufacturing on glass core substrates employs advanced photolithography and metallization techniques:

• Seed Layer Deposition: A thin adhesion/seed layer (titanium 5–20 nm / copper 100–500 nm or nickel-phosphorus alloy with P content <5 wt% / copper) is deposited by physical vapor deposition (PVD, sputtering power 2–10 kW, base pressure <1×10⁻⁶ Torr, deposition rate 0.5–5 nm/s) 12,13. Patent 13 specifies that nickel plating layers with phosphorus content ≤5 wt% reduce residual stress and minimize glass cracking risk 13.

• Photoresist Patterning: Positive-tone photoresist (thickness 2–10 μm, resolution <0.5 μm) is spin-coated (1000–3000 rpm, 30–60 s), soft-baked (90–110°C, 60–120 s), exposed using i-line (365 nm) or DUV (248 nm) lithography (dose 100–500 mJ/cm²), and developed in alkaline solution (TMAH 2.38 wt%, 60 s) 10,19.

• Copper Electroplating: Copper is electroplated into photoresist trenches using semi-additive process (SAP) or modified semi-additive process (mSAP). For fine lines (width 2 μm, space 2 μm), mSAP with ultra-thin seed layer (Cu <200 nm) and optimized plating chemistry (levelers, suppressors, accelerators) achieves line height 2–5 μm with sidewall angle 85–90° 10,19.

• Photoresist Stripping And Seed Etching: Photoresist is removed using oxygen plasma ashing (power 500–2000 W, O₂ flow 500–2000 sccm, pressure 0.5–2 Torr, time 5–20 min) followed by wet stripping (NMP-based solvent, 60–80°C, 10–30 min). Seed layer is etched using acidic copper etchant (H₂SO₄/H₂O₂) or alkaline permanganate solution 10,19.

Patent 10 describes a method where fine redistribution segments are first fabricated on a temporary carrier (glass or silicon wafer with release layer), segmented by laser dicing or mechanical sawing, and then transferred to a coarse redistribution structure via conductive connectors 10. This approach decouples fine-line processing from large-format substrate handling, improving yield and enabling use of high-resolution lithography tools (stepper or scanner with field size 26 mm × 33 mm) 10.

Dielectric Layer Formation And Planarization

Dielectric layers in fine line RDL structures typically use photosensitive polyimide (PSPI), polybenzoxazole (PBO), or benzocyclobutene (BCB):

• Material Selection: PSPI offers high resolution (≥2 μm via diameter), low CTE (30–50 ppm/°C), and good adhesion to glass and copper 19. PBO provides lower dielectric constant (εr = 2.8–3.2 at 1 GHz) and higher thermal stability (Tg >350°C) 19. BCB exhibits ultra-low dielectric constant (εr = 2.65) and dissipation factor (tan δ <0.001), ideal for high-frequency applications 11.

• Coating And Curing: Dielectric material is spin-coated (500–2000 rpm, thickness 2–20 μm), soft-baked (80–120°C, 2–10 min), exposed through photomask (dose 200–1000 mJ/cm² for PSPI), developed, and hard-cured (300–400°C, 1–3 h in nitrogen atmosphere) 10,19.

• Planarization: Chemical mechanical polishing (CMP) is applied to achieve surface roughness Ra <5 nm and thickness uniformity <±5% across 300 mm substrates, ensuring consistent photolithography performance for subsequent RDL layers 10.

Patent 19 emphasizes the use of photosensitive insulating layers on glass substrates to enable fine circuit pattern formation and reduce defects such as circuit separation 19. The photosensitive layer (thickness 5–30 μm) is directly patterned without requiring separate photoresist, simplifying the process and improving alignment accuracy (overlay error <1 μm) 19.

Edge Coating And Stress Management

Edge regions of glass core substrates are vulnerable to crack initiation due to stress concentration and handling damage. Patent 1 discloses an edge coating method using air pressing for profile control 1. A conformal coating material (e.g., epoxy resin with filler particles, viscosity 1000–10000 cP at 25°C) is dispensed around the substrate perimeter and pressed using an air bladder (pressure 0.1–0.5 MPa) to form a smooth, uniform edge coating (thickness 10–50 μm) with outer sidewall substantially parallel to the glass edge 1. This coating redistributes edge stress and prevents moisture ingress, improving reliability in humid environments (85°C/85% RH, 1000 h) 1.

Patent 2 describes a frame structure (material: stainless steel, aluminum alloy, or rigid polymer composite) surrounding the glass core substrate 2. The frame is adhesively bonded to the edge coating layer, providing mechanical reinforcement during handling, assembly, and testing operations 2. Finite element modeling shows that frame-reinforced substrates exhibit 3× higher resistance to edge crack propagation compared to unframed substrates 2.

Applications Of Fine Line Redistribution Glass Core Substrates In Advanced Packaging

High-Performance Computing (HPC) And Artificial Intelligence (AI) Processors

Fine line redistribution glass core substrates are critical enablers for heterogeneous integration of high-performance processors, high-bandwidth memory (HBM), and I/O chiplets. The ultra-high interconnect density (>10,000 I/O per mm²) and low electrical parasitics (inductance <10 pH, capacitance <50 fF per via) of glass core substrates support data rates >56 Gbps per lane and aggregate bandwidth >10 Tbps 4,16. Patent 4 describes a semiconductor package where a silicon bridge interposer is embedded in a cavity within the glass core substrate, enabling chip-to-chip communication with pitch <40 μm and latency <1 ns 4. The glass core provides mechanical support and global routing, while the silicon bridge handles fine-pitch die-to-die connections 4.

Patent 16 presents a package architecture integrating power delivery inductors within the glass core substrate 16. Coupled inductor structures (inductance 10–100 nH, quality factor Q >20 at 100 MHz) are formed by plating copper coils (line width 20–50 μm, thickness 30–100 μm) around magnetic cores (material: NiZn ferrite or FeSiCr alloy, permeability μr = 50–500) embedded in cavities within the glass core 16. This integration reduces voltage droop by 30–50% and enables fully integrated voltage regulators (FIVR) with efficiency >85% at 100 A output current 16. The glass core's high thermal conductivity (1.0–1.4 W/m·K for borosilicate glass) facilitates heat dissipation from inductors and power transistors 16.

5G And Millimeter-Wave (mmWave) Communication Systems

Glass core substrates with fine line RDL are ideal for 5G antenna