Glass Core Substrate For Optical Interconnects: Advanced Materials And Integration Strategies For High-Bandwidth Photonic Systems

Fundamental Material Properties And Structural Characteristics Of Glass Core Substrates For Optical Interconnects

Glass core substrates leverage the intrinsic advantages of glass materials—including low dielectric constant (typically ε_r = 4.0–6.5 at 1 GHz), high optical transparency in the near-infrared spectrum (transmission >95% at 1310 nm and 1550 nm wavelengths), and CTE values (3.0–9.0 ppm/°C) closely matched to silicon (2.6 ppm/°C)—to enable co-packaging of photonic integrated circuits (PICs) with electrical ICs 6. The glass core typically consists of borosilicate, aluminosilicate, or fused silica compositions, selected based on target CTE, processing temperature compatibility (up to 260°C for solder reflow operations 11), and refractive index requirements for waveguide confinement 16.

Key Material Attributes:

• Optical Transparency: Glass substrates exhibit minimal absorption losses (<0.1 dB/cm) at telecom wavelengths (1310 nm, 1550 nm), enabling efficient light propagation through embedded waveguides and vertical optical paths 16.
• Thermal Stability: Glass maintains dimensional stability and optical properties across temperature cycling (-40°C to +125°C), critical for automotive and industrial applications 11.
• Mechanical Rigidity: Young's modulus of 70–90 GPa provides structural support for multi-layer build-up structures while resisting warpage during high-temperature processing 410.
• Electrical Insulation: Volume resistivity >10¹⁴ Ω·cm ensures minimal signal crosstalk and leakage currents in dense routing architectures 8.

The glass core architecture typically comprises a single monolithic glass layer (200–500 µm thickness) or laminated multi-layer glass stacks bonded with low-CTE adhesive interlayers (e.g., epoxy-based bonding layers with CTE 30–50 ppm/°C) 714. Through-glass vias (TGVs) with diameters ranging from 20 µm to 100 µm are formed via laser drilling or wet etching, then metallized with copper or copper-tungsten alloys to provide vertical electrical interconnects 3812. The TGV sidewalls are often coated with a carbon-containing liner or nickel barrier layer (phosphorus content ≤5 mass% to minimize stress-induced cracking 11) to enhance adhesion and prevent copper diffusion into the glass matrix 811.

Optical Waveguide Integration And Photonic Coupling Mechanisms In Glass Core Substrates

Embedded optical waveguides constitute the core functional element enabling optical signal routing within glass substrates. These waveguides are fabricated by defining high-refractive-index core regions (n_core = 1.50–1.55) within the glass matrix, surrounded by lower-index cladding (n_clad = 1.46–1.48) to achieve total internal reflection 1613. Waveguide core materials include doped silica, polymer photodefinable materials, or ion-exchanged glass regions formed via potassium-sodium ion exchange processes 17.

Waveguide Fabrication Techniques:

• Photolithographic Patterning: Polymer waveguides are defined by spin-coating photodefinable materials (e.g., epoxy-acrylate resins) onto the glass surface, followed by UV exposure through photomasks and development to create core patterns with widths of 5–50 µm and heights of 30–80 µm 17.
• Laser Direct Writing: Femtosecond laser pulses induce localized refractive index changes (Δn ≈ 0.01–0.02) in the glass bulk, enabling three-dimensional waveguide routing without photomasks 1.
• Ion Exchange: Immersion of glass substrates in molten salt baths (e.g., KNO₃ at 350–450°C for 2–8 hours) replaces sodium ions with potassium ions, increasing the local refractive index by 0.02–0.05 to form buried waveguides 6.

Optical Coupling Architectures:

The glass interconnection substrate disclosed in 1 employs a curved waveguide geometry to redirect optical signals from horizontal substrate waveguides (propagating parallel to the substrate plane) to vertical optical paths coupling into PIC facets. The curved portion exhibits a bending radius of 5–20 mm to maintain low bending losses (<0.5 dB per 90° turn at 1550 nm) 1. The waveguide end surfaces are polished to optical-grade flatness (surface roughness <10 nm RMS) and positioned within ±1 µm alignment tolerance to the PIC coupling surface using passive alignment features (e.g., V-grooves, mechanical stops) or active alignment with sub-micron precision stages 16.

For vertical optical interconnects, the substrate incorporates optical vias or apertures etched through metallization layers, allowing light to traverse the glass core thickness and couple between photoelectric conversion devices (e.g., vertical-cavity surface-emitting lasers, photodetectors) mounted on opposite substrate surfaces 18. The aperture geometry is optimized (diameter 50–200 µm, sidewall angle 80–90°) to minimize Fresnel reflection losses (<4% per interface) and mode mismatch losses 18.

Through-Glass Via (TGV) Fabrication Processes And Metallization Strategies For Electrical Interconnects

Through-glass vias provide vertical electrical pathways essential for power delivery, ground distribution, and high-speed signal routing in glass core substrates. TGV fabrication involves sequential steps of via formation, sidewall treatment, barrier/seed layer deposition, and copper electroplating 3812.

TGV Formation Methods:

• Laser Drilling: CO₂ lasers (wavelength 10.6 µm) or ultrafast lasers (pulse duration <10 ps) ablate glass to create vias with aspect ratios up to 10:1 (depth:diameter). Laser parameters (fluence 5–20 J/cm², repetition rate 10–100 kHz) are tuned to minimize heat-affected zones and microcracks 4.
• Wet Chemical Etching: Glass substrates are patterned with etch-resistant masks (e.g., chromium, photoresist), then immersed in hydrofluoric acid (HF) solutions (5–20 wt%, 20–60°C, 10–120 minutes) to selectively dissolve exposed glass regions. Etch rates of 1–10 µm/min yield via depths of 100–500 µm with tapered sidewall profiles (taper angle 2–10°) 12.
• Mechanical Drilling: Ultrasonic or diamond-coated drill bits (diameter 50–300 µm) mechanically remove glass material, suitable for low-volume prototyping but prone to chipping and microcrack formation 12.

Metallization And Barrier Layer Engineering:

Following via formation, sidewalls are treated to enhance adhesion and prevent copper diffusion. A carbon-containing liner (deposited via plasma-enhanced chemical vapor deposition at 200–300°C, thickness 50–200 nm) provides a diffusion barrier and nucleation sites for subsequent metal deposition 8. Alternatively, electroless nickel plating (phosphorus content ≤5 mass%, thickness 0.5–2 µm) is applied, followed by electroless copper seed layer deposition (thickness 0.2–0.5 µm) 11. Electrolytic copper plating (current density 1–5 A/dm², plating time 30–180 minutes, bath temperature 25–35°C) fills the vias, achieving resistivity <2.0 µΩ·cm and void-free filling for aspect ratios up to 5:1 3812.

Singulation And Crack Mitigation:

Glass brittleness poses challenges during substrate singulation (dicing into individual packages). Laser-assisted singulation techniques create controlled laser-treated zones with increased nanoporosity (porosity 15–30% vs. <5% in untreated glass), facilitating crack propagation along predefined scribe lines while minimizing uncontrolled fracture 4. Alternatively, mechanical dicing with resin-bonded diamond blades (blade thickness 50–100 µm, spindle speed 20,000–40,000 rpm, feed rate 5–20 mm/s) is employed with edge reinforcement structures to prevent chipping 4.

Multi-Layer Build-Up Structures And Redistribution Layers For High-Density Routing In Glass Core Substrates

Glass core substrates support multi-layer build-up structures on both surfaces, enabling fine-pitch redistribution layers (RDLs) for fan-out routing and high-density interconnects. Build-up layers consist of alternating dielectric films (e.g., polyimide, benzocyclobutene, epoxy-based photoresists with dielectric constant 2.8–3.5 at 10 GHz, thickness 5–20 µm per layer) and patterned copper traces (line width/spacing 2/2 µm to 10/10 µm, thickness 3–10 µm) 236.

Build-Up Layer Fabrication Sequence:

1. Dielectric Deposition: Spin-coating or lamination of photosensitive dielectric films onto the glass core surface, followed by soft baking (80–120°C, 2–5 minutes) 2.
2. Via Formation: Photolithographic exposure and development to create microvias (diameter 10–50 µm) connecting to underlying TGVs or conductor patterns 23.
3. Seed Layer Sputtering: Physical vapor deposition of titanium/copper or tantalum/copper adhesion/seed layers (total thickness 100–300 nm) 3.
4. Copper Electroplating: Pattern plating using photoresist masks to define RDL traces, followed by seed layer etching 3.
5. Dielectric Curing: Thermal curing (200–350°C, 1–3 hours in nitrogen atmosphere) to achieve final mechanical and electrical properties 26.

Pre-Patterned Conductor Integration:

Advanced architectures incorporate pre-patterned electrically conductive interconnects within the glass core laminate stack prior to final assembly 2. Glass layers are individually processed with conductor patterns (formed via electroless nickel/electrolytic copper plating, line width 20–100 µm), then laminated with dielectric bonding layers (thickness 10–50 µm, CTE 30–50 ppm/°C) under controlled temperature (150–250°C) and pressure (0.5–5 MPa) to form a monolithic multi-layer core 2714. This approach enables higher wiring density (>1000 interconnects/cm²) and reduced parasitic capacitance compared to post-lamination via drilling 2.

Applications Of Glass Core Substrates In High-Bandwidth Optical Interconnect Systems

Co-Packaging Of Photonic Integrated Circuits And Switching ASICs For Data Center Infrastructure

Glass core substrates enable co-packaging of silicon photonic transceivers with electrical switching ASICs, reducing electrical interconnect lengths for 56 Gbps and higher data rates while maintaining signal integrity 6. The substrate provides both optical waveguide routing (for chip-to-fiber and chip-to-chip optical links) and high-density electrical redistribution layers (for power delivery and low-speed control signals) within a single platform 6. Typical configurations position the PIC die on the substrate's upper surface, with optical waveguides embedded in the glass core routing signals to edge-coupled fiber connectors or vertical grating couplers 16. The switching ASIC is mounted on the same or opposite substrate surface, interconnected via TGVs and RDLs with signal path lengths <5 mm to minimize propagation delay (<25 ps) and insertion loss (<1 dB at 56 GHz) 6.

Performance Metrics:

• Optical Coupling Efficiency: >80% coupling efficiency between PIC waveguides and substrate waveguides, achieved through mode-matching tapered waveguide designs and anti-reflection coatings 16.
• Electrical Signal Integrity: Insertion loss <2 dB and return loss >15 dB for 56 Gbps PAM-4 signals routed through TGVs and RDLs, measured via vector network analyzer characterization 6.
• Thermal Management: Glass core thermal conductivity (1.0–1.4 W/m·K) combined with integrated thermal vias (copper-filled TGVs with diameter 100–200 µm, pitch 500–1000 µm) maintains junction temperatures <85°C under 50 W total power dissipation 6.

Silicon Bridge Interposer Integration For Multi-Die Heterogeneous Packages

Glass core substrates serve as the primary structural platform for heterogeneous integration, with localized silicon bridge interposers embedded in cavities formed in the glass core to provide ultra-high-density chip-to-chip interconnects 5. The silicon bridge (thickness 50–100 µm, area 5×5 mm² to 10×20 mm²) contains fine-pitch through-silicon vias (TSVs, diameter 5–10 µm, pitch 20–40 µm) and micro-bump pads (diameter 20–40 µm, pitch 40–80 µm) enabling direct die-to-die communication at bandwidths exceeding 1 Tbps 5. The glass core cavity is formed via laser ablation or mechanical milling (depth 50–150 µm, tolerance ±10 µm), and the silicon bridge is adhesively bonded into the cavity using epoxy underfill materials (CTE 25–40 ppm/°C, glass transition temperature T_g >150°C) 5. Multi-layer wiring layers beneath the glass core and silicon bridge provide global routing and connection to external solder balls (diameter 300–500 µm, pitch 0.5–1.0 mm) for board-level assembly 5.

Integration Advantages:

• Minimized Interposer Size: Silicon bridge area reduced by 60–80% compared to full-area silicon interposers, lowering material costs and improving yield 5.
• Warpage Control: Glass core rigidity (flexural modulus 70–90 GPa) limits package warpage to <50 µm over 40×40 mm² substrate area during reflow (peak temperature 260°C), ensuring reliable solder joint formation 510.
• CTE Matching: Glass CTE (3.0–5.0 ppm/°C) closely matches silicon (2.6 ppm/°C) and silicon bridge CTE, minimizing thermomechanical stress and solder fatigue during temperature cycling (-40°C to +125°C, >1000 cycles) 5.

Optical-Electrical Substrates For Flip-Chip Photonic Device Assembly

Optical-electrical substrates integrate glass optical waveguides along the upper surface with electrically conductive TGVs extending from an intermediate surface to the lower surface, enabling simultaneous optical and electrical connections to flip-chip mounted PICs 6. The intermediate surface (positioned 100–300 µm below the upper surface) supports redistribution layers and optional electrical ICs (e.g., transimpedance amplifiers, laser drivers), while the lower surface provides solder ball pads for board-level interconnection 6. Flip-chip assembly employs gold or copper bonding bumps (diameter 30–80 µm, height 15–40 µm) reflowed at 260–280°C to form mechanical and electrical bonds, with alignment tolerances ±2 µm achieved via passive alignment features or active vision-based alignment 6.

Optical Coupling Strategies:

• Edge Coupling: PIC waveguide facets (mode field diameter 3–