Heterogeneous Integration Glass Core Substrate: Advanced Architectures, Manufacturing Processes, And Applications In High-Density IC Packaging

Fundamental Material Properties And Structural Characteristics Of Heterogeneous Integration Glass Core Substrate

Heterogeneous integration glass core substrate architectures leverage the intrinsic properties of glass materials to overcome limitations inherent in conventional copper-clad laminate (CCL) cores. The glass core typically comprises borosilicate, aluminosilicate, or photosensitive glass compositions, selected based on application-specific requirements for dielectric constant (Dk), dissipation factor (Df), and thermal stability 23. Key material properties include:

• Coefficient of Thermal Expansion (CTE): Glass cores exhibit CTE values in the range of 3–7 ppm/°C, closely matching silicon IC dies (2.6 ppm/°C), thereby minimizing thermomechanical stress during assembly and thermal cycling 113. This CTE compatibility is critical for preventing solder joint fatigue and die cracking in flip-chip configurations.

• Total Thickness Variation (TTV): Glass substrates achieve TTV values below 5 μm across 300 mm panels, compared to 20–50 μm for organic CCL cores 13. Low TTV eliminates the need for costly planarization processes in build-up layer fabrication and ensures uniform solder bump heights for high-yield assembly.

• Dielectric Properties: Typical glass core materials provide Dk values of 4.5–6.5 at 1 GHz and Df < 0.005, enabling low signal loss and minimal crosstalk in high-frequency applications 78. Photosensitive glass substrates can achieve even lower Dk (3.8–4.2) through controlled crystallization processes 710.

• Mechanical Modulus: Glass cores exhibit Young's modulus values of 70–90 GPa, providing superior stiffness compared to organic substrates (15–25 GPa) and reducing package warpage during reflow and underfill curing 1316.

The structural architecture of heterogeneous integration glass core substrate typically consists of a central glass core layer (100–800 μm thickness) with through-glass vias (TGVs) providing vertical electrical interconnection, sandwiched between multiple build-up layers comprising alternating dielectric and metallization patterns 236. Advanced architectures incorporate multi-layer glass cores with intermediate bonding layers to enable thicker substrates while maintaining TGV aspect ratio feasibility 4617.

Through-Glass Via (TGV) Formation Technologies And Conductive Filling Processes

TGV fabrication represents a critical enabling technology for heterogeneous integration glass core substrate, with via formation methods and metallization processes directly impacting electrical performance, reliability, and manufacturing yield. Multiple TGV formation approaches have been developed:

Laser Drilling And Ablation Techniques

Laser drilling using ultraviolet (UV) or infrared (IR) wavelength systems enables rapid via formation with diameters ranging from 30 μm to 200 μm 18. However, laser-drilled vias in thick glass cores (>400 μm) exhibit severe taper angles (5–15°), limiting achievable aspect ratios to approximately 3:1 13. This taper constraint necessitates larger via capture pad dimensions, reducing routing density. Recent innovations incorporate carbon-based sidewall liners deposited via chemical vapor deposition (CVD) to improve adhesion between glass and subsequent metallization 8.

Photosensitive Glass Patterning

Photosensitive glass substrates enable direct photolithographic patterning of via structures through a multi-step process: UV exposure through a photomask, thermal activation at 500–600°C to induce selective crystallization, and wet chemical etching in dilute hydrofluoric acid (HF) solutions 710. This approach achieves near-vertical sidewall profiles (taper <2°) and aspect ratios exceeding 10:1, with via diameters as small as 10 μm 7. The resulting glass-ceramic composite structure provides enhanced mechanical strength while maintaining low dielectric loss.

Mechanical Drilling And Ultrasonic Machining

For larger via diameters (>300 μm) and lower aspect ratios, mechanical drilling with diamond-coated bits or ultrasonic machining offers cost-effective alternatives 46. These methods minimize thermal stress but require careful control of drilling parameters to prevent microcracking at via edges.

TGV Metallization And Conductive Filling

Following via formation, metallization processes establish electrical conductivity through the glass core. Common approaches include:

• Electroless Copper Seed Layer Deposition: A thin (0.5–2 μm) electroless copper layer is deposited on via sidewalls following surface activation with palladium catalysts 238. This seed layer enables subsequent electrolytic copper plating to fill the via.

• Electrolytic Copper Plating: Vias are filled with copper using acid copper sulfate electrolytes under controlled current density (1–5 A/dm²) and plating additives to minimize voiding 28. For high aspect ratio vias (>5:1), pulse-reverse plating or periodic dummy plating techniques prevent via closure before complete filling.

• Dielectric Buffer Layers: Advanced architectures incorporate thin (50–500 nm) dielectric buffer layers (silicon dioxide, silicon nitride, or spin-on glass) between the glass sidewall and copper fill to mitigate CTE mismatch stress and improve reliability 914. These buffer layers reduce interfacial stress by 30–50% during thermal cycling, as demonstrated in accelerated reliability testing 9.

• Alternative Conductive Materials: For specialized applications, silver, gold, or conductive polymer fills may be employed, particularly in RF/microwave systems where skin effect losses favor noble metals 710.

Multi-Layer Glass Core Architectures And Hybrid Substrate Configurations

To address the limitations of single-layer glass cores in thick substrate applications, multi-layer glass core architectures have been developed, enabling substrate thicknesses exceeding 1 mm while maintaining TGV aspect ratio feasibility 461317.

Bonded Multi-Layer Glass Structures

Multi-layer glass core substrates comprise two or more discrete glass layers (typically 200–400 μm each) bonded together using intermediate adhesive or glass-frit bonding layers 4617. The bonding process typically involves:

• Surface Preparation: Glass surfaces are cleaned and activated using plasma treatment or wet chemical processes to enhance bonding strength 417.

• Bonding Layer Application: Adhesive materials (epoxy, polyimide, or benzocyclobutene) or glass-frit pastes are applied with controlled thickness (5–20 μm) 417. Glass-frit bonding, performed at 400–600°C, provides superior thermal stability and CTE matching compared to organic adhesives.

• Lamination And Curing: Bonded stacks are subjected to pressure (0.5–2 MPa) and elevated temperature (150–600°C depending on bonding material) to achieve full consolidation 4617.

• TGV Formation Through Bonded Stack: Following bonding, TGVs are formed through the entire multi-layer stack using laser drilling or mechanical drilling, with subsequent metallization processes identical to single-layer cores 4617.

This approach enables substrate thicknesses of 800–1200 μm with TGV aspect ratios maintained below 5:1, facilitating integration of thicker IC dies and passive components 46.

Hybrid Glass-Organic Core Architectures

Hybrid core configurations combine glass layers with organic dielectric layers (prepreg or resin-coated copper) to balance the advantages of glass (low TTV, high modulus) with the processing flexibility of organic materials 1315. A typical hybrid core comprises alternating glass layers (100–200 μm) and organic dielectric layers (50–100 μm), with through-hole vias extending through the entire stack 13. This architecture reduces overall material cost by 20–40% compared to all-glass cores while maintaining TTV below 10 μm 13. The hybrid approach also simplifies via formation, as organic layers can be drilled using conventional mechanical or laser drilling without the taper issues associated with thick glass 13.

Glass-Ceramic Composite Cores

Glass-ceramic composite cores integrate glass woven fabric reinforcement within a glass-ceramic sintered matrix, combining the dimensional stability of glass with enhanced fracture toughness 15. The fabrication process involves impregnating glass fabric with a slurry containing glass powder and metal oxide additives (alumina, zirconia), followed by co-firing at 800–1000°C to achieve full densification 15. The resulting composite exhibits flexural strength 2–3× higher than monolithic glass while maintaining CTE below 6 ppm/°C 15.

Build-Up Layer Integration And Interconnect Density Optimization For Heterogeneous Integration Glass Core Substrate

The integration of build-up layers on glass core substrates enables fine-pitch interconnect routing and die attachment interfaces, with layer count typically ranging from 2–6 layers per side depending on routing complexity 231416.

Build-Up Dielectric Material Selection

Build-up dielectric materials must provide:

• CTE Compatibility: Dielectric CTE should be matched to the glass core (3–7 ppm/°C) to minimize interfacial stress and prevent delamination 1416. Spin-on glass (SOG) dielectrics containing silicon, oxygen, and dopants (boron, phosphorus) achieve CTE values of 4–6 ppm/°C with excellent adhesion to glass surfaces 14.

• Low Moisture Absorption: Moisture uptake below 0.1% is required to maintain dimensional stability and prevent popcorn cracking during reflow 214. SOG and low-k organic dielectrics (benzocyclobutene, polyimide) meet this requirement.

• Thermal Stability: Build-up dielectrics must withstand multiple reflow cycles at 260°C without degradation 214. Glass transition temperatures (Tg) above 300°C are preferred.

• Dielectric Properties: For high-frequency applications, build-up dielectrics with Dk < 3.5 and Df < 0.01 minimize signal loss 714.

Metallization Patterning And Via Formation In Build-Up Layers

Build-up layer metallization employs semi-additive processes (SAP) or modified semi-additive processes (mSAP) to achieve line/space dimensions of 2/2 μm to 10/10 μm 2314. The process sequence includes:

• Dielectric Layer Application: Liquid dielectric materials are spin-coated or laminated onto the glass core or previous build-up layer, followed by curing at 150–250°C 14.

• Via Formation: Microvias (10–50 μm diameter) are formed using laser ablation (CO₂ or UV lasers) or photolithographic patterning for photosensitive dielectrics 214.

• Desmear And Activation: Via surfaces are cleaned using permanganate or plasma desmear processes, followed by palladium activation for electroless copper deposition 214.

• Copper Seed Layer And Plating: A thin (0.3–1 μm) electroless copper seed layer is deposited, followed by photoresist patterning and electrolytic copper plating (8–15 μm thickness) to form traces and via fills 214.

• Photoresist Strip And Flash Etching: Photoresist is removed, and the seed layer is flash-etched to define final trace patterns 214.

Stress Mitigation Strategies In Build-Up Layer Integration

Compressive stress from build-up layers can induce catastrophic failure in glass cores, particularly at panel edges during singulation 16. Stress mitigation architectures include:

• Stress Relief Slots: Narrow slots (50–200 μm width) are laser-cut into build-up layers near panel edges to interrupt stress propagation pathways, reducing edge stress by 40–60% 16.

• Compliant Interlayers: Thin (5–20 μm) compliant polymer layers with low modulus (0.5–2 GPa) are inserted between the glass core and build-up layers to absorb differential thermal expansion stress 16.

• Graded CTE Build-Up Stacks: Build-up layer CTE is progressively graded from glass-matched values (4–6 ppm/°C) near the core to higher values (15–25 ppm/°C) in outer layers, reducing interfacial stress concentrations 16.

Cavity Structures And Embedded Die Integration In Heterogeneous Integration Glass Core Substrate

Advanced heterogeneous integration architectures incorporate cavity structures within the glass core to enable embedded die integration, reducing package thickness and improving electrical performance through shortened interconnect paths 511.

Blind Cavity And Through-Cavity Configurations

Glass core cavities are formed using laser ablation, mechanical milling, or wet etching processes, with cavity depths ranging from 50 μm to full substrate thickness 511. Two primary configurations exist:

• Blind Cavities: Cavities extend partially through the glass core from one surface, providing recessed die mounting locations while maintaining continuous glass on the opposing surface 5. This configuration is preferred for applications requiring high mechanical strength and simplified build-up layer processing.

• Through-Cavities: Cavities extend completely through the glass core, enabling die placement with both front and back surfaces accessible for interconnection 5. Through-cavity designs facilitate heterogeneous integration of dies with through-silicon vias (TSVs), enabling vertical signal routing through the embedded die.

Embedded Die Interconnection Strategies

IC dies embedded within glass core cavities are electrically coupled to substrate routing through multiple approaches:

• Lateral Interconnection: Embedded dies provide lateral electrical coupling between adjacent dies mounted on the substrate surface, with interconnection through TGVs and build-up layer routing 5. This configuration is used for interposer applications where the embedded die serves as a high-density routing bridge.

• Vertical Interconnection: Embedded dies with TSVs enable vertical signal routing from the substrate's top surface to bottom surface, with the embedded die functioning as an active interposer 5. This approach reduces signal path length by 30–50% compared to peripheral routing, improving signal integrity at frequencies above 10 GHz.

• Hybrid Lateral-Vertical Interconnection: Combined lateral and vertical routing through embedded dies enables complex heterogeneous integration of multiple die types (logic, memory, RF) with optimized signal paths for each functional block 5.

Cavity Filling And Planarization

Following die placement, cavities are filled with underfill or molding compound to provide mechanical support and environmental protection 511. Capillary underfill materials (epoxy-based, CTE 20–40 ppm/°C) are dispensed around die edges and drawn into gaps by capillary action, with curing at 150–180°C 5. For larger cavities, compression molding with epoxy molding compound provides void-free filling and co-planar surfaces for subsequent build-up layer processing 11.

Singulation Processes And Edge Quality Control For Heterogeneous Integration Glass Core Substrate

Substrate singulation represents a critical process step, as glass brittleness necessitates specialized dicing approaches to prevent chipping, cracking, and delamination 116.

Laser-Assisted Singulation Techniques

Laser singulation employs focused laser beams to induce controlled fracture along predefined scribe lines 1. The process creates localized laser-treated areas with increased nanoporosity (2–5× higher than bulk glass), reducing fracture toughness and enabling clean separation 1. Key process parameters include:

• Laser Wavelength And Power: UV lasers (355 nm) at 5–15 W average power provide optimal energy absorption in glass with minimal thermal damage to adjacent build-up layers 1.

• Pulse Repetition Rate: High repetition rates (50–200 kHz) enable rapid processing while maintaining controlled crack propagation 1.

• Scribe Line Spacing: Multiple parallel laser scribe lines spaced 50–200 μm apart create a weakened zone that facilitates mechanical breaking with reduced edge chipping 1.

Mechanical Dicing With Diamond Blades

For thicker substrates (>600 μm) or