2.5D Packaging Glass Core Substrate: Advanced Architectures, Manufacturing Processes, And Performance Optimization For High-Density Semiconductor Integration

Structural Composition And Core Via Engineering Of 2.5D Packaging Glass Core Substrate

The fundamental architecture of a 2.5D packaging glass core substrate comprises a glass substrate with precisely engineered through-glass vias (TGVs), a core distribution layer providing electrical connectivity, and upper buildup layers interfacing with semiconductor dies 14. The glass substrate typically features a first surface and a second surface facing each other, with core vias penetrating through the entire thickness to establish vertical electrical pathways 38. These core vias represent the critical structural element enabling high-density interconnection while maintaining the mechanical integrity and dimensional stability inherent to glass materials.

Core Via Dimensional Control And Distribution Uniformity

Achieving precise control over core via geometry is paramount for ensuring reliable electrical performance and manufacturing yield in 2.5D packaging glass core substrates. According to patent documentation, the average inner diameter of the minimum cross-section within a core via typically ranges from 50 μm to 95 μm, with stringent requirements on diameter distribution uniformity 1. The dimensional consistency is quantified through the relationship (D90 - D10) / D50 ≤ 0.3, where D50, D90, and D10 represent the 50th, 90th, and 10th percentile values in the diameter distribution of the minimum inner diameter, respectively 1. More advanced implementations achieve even tighter control with (D90 - D10) / D50 ≤ 0.2, ensuring minimal variation across large-area substrates 1.

The opening diameters at the first and second surfaces of the glass substrate exhibit larger dimensions than the minimum inner diameter, creating a tapered via profile. The target opening diameter (defined as the larger of the first surface opening diameter and second surface opening diameter) typically ranges from 70 μm to 120 μm 1. This tapered geometry facilitates subsequent metallization processes while maintaining structural integrity during thermal cycling and mechanical stress. For cavity-integrated designs, the tapered angle of recessed cavity portions is precisely controlled between 86 degrees and 90 degrees to optimize die embedding and thermal interface performance 2.

Multi-Layer Glass Lamination And Bonding Interface Engineering

Advanced 2.5D packaging glass core substrates frequently employ multi-layer glass lamination to achieve enhanced mechanical properties and enable complex via architectures. A representative structure comprises a first glass layer, a second glass layer, and a third glass layer sequentially stacked with intermediate bonding layers 11. The first bonding layer is disposed between the first and second glass layers, while the second bonding layer is positioned between the second and third glass layers, creating a composite structure with superior fracture resistance and dimensional stability 11.

The bonding interface between laminated glass layers requires careful engineering to minimize stress concentration and prevent delamination during thermal excursions. Stress management is quantified through the parameter P = Vp - Np, where Vp represents the difference between maximum and minimum stress measured along a via line (connecting core via locations) and Np represents the corresponding stress difference along a plain line (connecting regions without vias) 3. High-performance substrates achieve P ≤ 1.5 MPa, indicating minimal stress perturbation introduced by via formation and ensuring long-term reliability under thermal and mechanical loading 3.

Core Distribution Layer And Metallization Architecture

The core distribution layer constitutes the electrically conductive infrastructure that interconnects the first and second surfaces of the glass substrate through the core vias 148. This layer comprises electrically conductive material disposed on at least a portion of the first surface, the second surface, and the interior walls of the core vias, establishing continuous electrical pathways for signal transmission and power delivery. The metallization scheme typically begins with a core seed layer—a thin conductive film serving as the nucleation surface for subsequent electroplating or electroless plating processes 4.

The thickness of the core distribution layer is optimized to balance electrical resistance, mechanical reliability, and manufacturing feasibility. In high-performance implementations, the thickness of the thinner electrically conductive layer within the core distribution layer is designed to be equal to or greater than the width of the thinner electrically conductive layer in the upper buildup layers 8. This design principle ensures that the core layer does not become the limiting factor for current-carrying capacity and minimizes resistive losses in vertical interconnects. Substrates meeting this criterion can achieve resistance values of approximately 27.5 × 10⁻⁶ Ω or less when measured on a 100 μm × 100 μm cross-sectional area 8.

Manufacturing Processes And Fabrication Methodologies For Glass Core Substrates

The production of 2.5D packaging glass core substrates involves a sophisticated sequence of processes including glass substrate preparation, via formation, metallization, buildup layer fabrication, and final assembly. Each process step requires precise control of parameters such as temperature, pressure, chemical composition, and processing time to achieve the dimensional accuracy and material properties necessary for high-performance semiconductor packaging.

Glass Substrate Selection And Preparation

The selection of appropriate glass composition is fundamental to achieving the desired combination of mechanical strength, thermal stability, coefficient of thermal expansion (CTE) matching, and dielectric properties. Borosilicate glasses and aluminosilicate glasses are commonly employed due to their low CTE (typically 3-5 ppm/°C), high Young's modulus (70-90 GPa), and excellent dimensional stability across the operating temperature range of semiconductor devices 413. The glass substrate thickness typically ranges from 100 μm to 500 μm, with thinner substrates enabling more compact package profiles while thicker substrates provide enhanced mechanical rigidity for large-area panels.

Surface preparation of the glass substrate involves cleaning, planarization, and surface treatment to ensure optimal adhesion of subsequent layers. Chemical cleaning processes remove organic contaminants and particulates, while plasma treatment or chemical functionalization modifies the surface chemistry to promote adhesion of seed layers and bonding materials. For multi-layer laminated structures, the bonding surfaces undergo specialized preparation to achieve high bond strength and minimize interfacial defects 11.

Through-Glass Via Formation Technologies

Through-glass via (TGV) formation represents one of the most critical and technically challenging steps in glass core substrate manufacturing. Multiple technologies have been developed for creating vias in glass substrates, each with distinct advantages and limitations:

Laser Drilling: Ultrafast laser ablation using picosecond or femtosecond laser pulses enables precise via formation with minimal thermal damage to surrounding glass material 12. The laser drilling process can achieve via diameters as small as 20-50 μm with high aspect ratios (depth-to-diameter ratio) exceeding 5:1. Process parameters including laser wavelength, pulse duration, repetition rate, and scanning strategy are optimized to control via profile, taper angle, and surface roughness. Multi-pass drilling strategies with progressively adjusted parameters enable creation of the characteristic tapered profile with controlled opening diameters and minimum inner diameter 1.

Wet Chemical Etching: Hydrofluoric acid (HF)-based wet etching processes provide an alternative approach for via formation, particularly for larger diameter vias and applications requiring smooth via sidewalls 3. The etching process typically employs photolithographically defined etch masks and controlled immersion in HF solutions with concentrations ranging from 5% to 49% at temperatures between 20°C and 60°C. Etching rates depend on glass composition, HF concentration, temperature, and agitation, with typical rates ranging from 1-10 μm/min. The isotropic nature of wet etching naturally produces tapered via profiles, with the taper angle controlled through etch time and mask geometry.

Mechanical Drilling: For larger diameter vias (>200 μm) and lower density applications, mechanical drilling using diamond-coated drill bits or ultrasonic machining provides a cost-effective solution 5. However, mechanical drilling introduces higher risk of micro-cracking and edge chipping, necessitating subsequent surface treatment and inspection processes.

Metallization And Electrical Interconnect Formation

Following via formation, the glass substrate undergoes metallization to create the electrically conductive pathways required for signal transmission and power delivery. The metallization process typically comprises multiple sequential steps:

Seed Layer Deposition: A thin conductive seed layer (typically 50-200 nm thickness) is deposited on the glass surfaces and via sidewalls using physical vapor deposition (PVD) techniques such as sputtering or evaporation 48. Common seed layer materials include titanium/copper (Ti/Cu), chromium/copper (Cr/Cu), or titanium/tungsten/copper (Ti/W/Cu) stacks, where the adhesion layer (Ti, Cr, or Ti/W) promotes bonding to the glass surface and the copper layer serves as the conductive base for subsequent electroplating. The seed layer deposition process must achieve conformal coverage of the via sidewalls, including the tapered regions and minimum diameter sections, to ensure continuous electrical connectivity.

Electroplating: Copper electroplating fills the vias and builds up the conductive traces on the glass surfaces 14. The electroplating process employs acidic copper sulfate electrolytes with organic additives (accelerators, suppressors, and levelers) to control deposition rate, throwing power, and surface morphology. Plating parameters including current density (1-5 A/dm²), temperature (20-30°C), and agitation are optimized to achieve complete via filling without voids or seams. For vias with high aspect ratios or complex geometries, pulse plating or periodic reverse plating techniques may be employed to enhance filling uniformity. The final copper thickness on the glass surfaces typically ranges from 5 μm to 30 μm, depending on current-carrying requirements and subsequent processing steps 8.

Surface Finishing: Following bulk copper plating, surface finishing processes such as chemical mechanical polishing (CMP) planarize the metallized surfaces and remove excess copper, creating a smooth, flat surface suitable for subsequent buildup layer fabrication 5. Alternative finishing approaches include electroless nickel/immersion gold (ENIG) or organic solderability preservative (OSP) coatings to protect copper surfaces and provide solderable terminations.

Buildup Layer Fabrication And Integration

The upper and lower buildup layers provide the fine-pitch redistribution routing that connects the core distribution layer to the semiconductor dies and external package interconnects 148. Buildup layer fabrication employs sequential lamination and patterning of dielectric films and conductive traces:

Dielectric Layer Application: Organic dielectric materials such as epoxy-based films, polyimide, or polybenzoxazole (PBO) are laminated or spin-coated onto the metallized glass core 4. The dielectric thickness typically ranges from 5 μm to 30 μm per layer, with multiple layers stacked to achieve the required routing density and electrical isolation. The dielectric materials are selected to provide low dielectric constant (εr = 2.5-4.0), low dissipation factor (tan δ < 0.01), high glass transition temperature (Tg > 200°C), and CTE matching to the glass core and semiconductor dies.

Via Formation And Metallization: Microvias connecting successive buildup layers are formed using laser ablation (typically CO₂ or UV lasers) or photolithographic processes 4. The microvias are then metallized using seed layer deposition and copper electroplating, following similar processes as the core via metallization but optimized for smaller dimensions (typically 20-50 μm diameter). Advanced implementations employ stacked or staggered microvia architectures to minimize signal path length and reduce parasitic inductance.

Trace Patterning: Conductive traces in each buildup layer are defined using subtractive (etch-back) or semi-additive (SAP) processes 4. The semi-additive process, which involves thin seed layer deposition, photoresist patterning, selective copper plating, resist stripping, and seed layer etching, enables finer line/space dimensions (typically 2-10 μm) compared to subtractive processes. The trace width and spacing are optimized based on electrical requirements, with critical signal traces designed to achieve controlled impedance (typically 40-60 Ω for single-ended signals, 80-120 Ω for differential pairs).

Die Embedding And Cavity Integration

For advanced 2.5D packaging architectures, semiconductor dies are embedded within cavities formed in the glass core substrate, enabling ultra-compact package profiles and minimized interconnect lengths 2613. The cavity formation process involves:

Cavity Machining: Recessed cavities are created in the glass substrate using laser ablation, mechanical milling, or wet etching processes 2. The cavity depth is precisely controlled to match the die thickness, with typical depths ranging from 50 μm to 300 μm. The cavity sidewalls exhibit a controlled taper angle (86-90 degrees) to facilitate die placement and underfill flow 2.

Die Placement And Bonding: Semiconductor dies are placed into the cavities and bonded to the metal array or redistribution layer at the cavity bottom using solder reflow, thermocompression bonding, or adhesive bonding processes 6. The bonding process must achieve reliable electrical connectivity and mechanical attachment while minimizing thermal stress and warpage.

Underfill And Encapsulation: Following die bonding, underfill materials are dispensed to fill the gap between the die and cavity sidewalls, providing mechanical support and stress relief 6. Capillary underfill or molded underfill processes are employed depending on cavity geometry and production volume requirements. The underfill material is selected to provide CTE matching, high glass transition temperature, and low moisture absorption.

Electrical Performance Characteristics And Signal Integrity Optimization

The electrical performance of 2.5D packaging glass core substrates is characterized by multiple parameters including resistance, capacitance, inductance, signal propagation delay, insertion loss, and crosstalk. These parameters directly impact the operating frequency, power consumption, and signal integrity of the integrated semiconductor system.

Resistance And Current-Carrying Capacity

The electrical resistance of interconnects in glass core substrates is determined by the conductor geometry, material resistivity, and current distribution. For a substrate with 100 μm × 100 μm cross-sectional area, high-performance implementations achieve resistance values of approximately 27.5 × 10⁻⁶ Ω or less 8. This low resistance is achieved through optimized metallization thickness, high-purity copper (resistivity ≈ 1.7 × 10⁻⁸ Ω·m at 20°C), and minimized interface resistance between seed layers and plated copper.

The current-carrying capacity of core vias and redistribution traces is limited by electromigration and Joule heating effects. For continuous DC current, the maximum current density is typically limited to 1-2 × 10⁶ A/cm² to ensure long-term reliability (>10 years at operating temperature). For pulsed or AC signals, higher instantaneous current densities (up to 5 × 10⁶ A/cm²) may be tolerated depending on duty cycle and thermal management. The design of power delivery networks in glass core substrates must account for both DC resistance (IR drop) and AC impedance to ensure stable voltage supply to high-performance dies.

Capacitance And Dielectric Properties

The dielectric properties of glass core substrates significantly influence signal propagation characteristics and power integrity. Glass materials typically exhibit dielectric constant (εr) values ranging from 4.0 to 7.0 and dissipation factor (tan δ) values below 0.01 at frequencies up to several GHz 413. These properties compare favorably to organic substrates (εr = 3.5-4.5) and ceramic substrates (εr = 9-10), providing a balanced combination of signal velocity and impedance control.

The parasitic capacitance between adjacent signal traces and between signal traces and ground planes is minimized through careful routing design and dielectric thickness optimization. For a typical buildup layer with 10 μm dielectric thickness and εr = 3.5, the capacitance per unit length between parallel traces (assuming 5 μm width, 5 μm spacing) is approximately 0.1-0.2 pF/mm. This low parasitic capacitance enables high-speed signal transmission with minimal crosstalk and power consumption.

Inductance And High-Frequency Performance

The parasitic inductance of interconnects in glass core substrates affects signal rise time, ringing, and electromagnetic interference (EMI). Through-glass vias exhibit lower inductance compared to wire bonds or traditional package vias due to their shorter length and larger diameter. A typical core via with 50 μm