3D Packaging Glass Core Substrate: Advanced Material Solutions For High-Density Semiconductor Integration

Structural Composition And Material Characteristics Of 3D Packaging Glass Core Substrate

The fundamental architecture of a 3D packaging glass core substrate comprises a central glass layer sandwiched between overlying and underlying buildup layers, with electrically conductive vias penetrating the glass core to establish vertical interconnections 25. The glass core typically features a first surface and a second surface in parallel opposition, with thickness ranging from 30 µm to 500 µm depending on application requirements and mechanical design constraints 16.

Core Material Properties:

• Elastic Modulus: Glass cores exhibit elastic modulus values between 70 GPa and 90 GPa, significantly higher than organic substrates (typically 15-25 GPa), providing superior stiffness and dimensional stability during thermal cycling 513
• Coefficient of Thermal Expansion (CTE): Glass materials demonstrate CTE values in the range of 3-5 ppm/°C, closely matching silicon (2.6 ppm/°C) and minimizing thermomechanical stress at die-substrate interfaces 813
• Dielectric Constant: Glass substrates possess dielectric constant (Dk) values between 4.5 and 6.5 at 1 GHz, with dissipation factor (Df) below 0.01, enabling superior signal integrity for high-frequency applications 29
• Thermal Stability: Glass cores maintain structural integrity and electrical properties across operating temperature ranges from -55°C to +260°C, with glass transition temperature (Tg) exceeding 500°C for borosilicate compositions 13

The glass core is typically fabricated from borosilicate glass, aluminosilicate glass, or alkali-free glass compositions, selected based on CTE matching requirements, chemical resistance, and laser processing compatibility 613. Surface treatment of the glass core is critical for adhesion promotion with buildup layers, commonly involving plasma activation, silane coupling agents, or thin-film seed layer deposition to enhance interfacial bonding strength 713.

Via Formation Technologies And Metallization Strategies For Glass Core Substrates

Through-glass vias (TGVs) constitute the critical vertical interconnect structures in 3D packaging glass core substrates, enabling electrical coupling between routing layers on opposite surfaces of the glass core 267. Via formation in glass substrates presents unique challenges compared to organic materials due to glass's chemical inertness and brittleness.

Laser-Assisted Etching Process For Via Formation

The predominant method for TGV fabrication employs laser-assisted etching, combining laser ablation with chemical etching to achieve controlled via geometry 57. This process typically involves:

1. Laser Irradiation: Ultrafast laser pulses (picosecond or femtosecond regime) locally modify the glass structure, creating regions of enhanced etchability through densification or micro-cracking 7
2. Chemical Etching: Hydrofluoric acid (HF) or buffered oxide etchant (BOE) selectively removes laser-modified regions, forming via openings with aspect ratios up to 10:1 7
3. Surface Conditioning: Post-etch cleaning and surface activation prepare via sidewalls for subsequent metallization 7

Laser-assisted etching produces tapered via profiles with sidewall angles typically between 5° and 15° from vertical, which facilitates subsequent metallization but requires careful design consideration for via capture pad dimensions 7. Via diameters range from 20 µm to 100 µm, with pitch capabilities down to 40 µm enabling high-density interconnect architectures 26.

Metallization Approaches For Through-Glass Vias

Metallization of TGVs with high aspect ratios and tapered sidewalls necessitates specialized deposition techniques beyond conventional physical vapor deposition (PVD) 7. Two primary metallization strategies are employed:

Electroless Seed Layer Deposition:

Electroless plating provides conformal seed layer coverage on complex via geometries, addressing limitations of line-of-sight PVD processes 7. The electroless deposition process involves:

• Surface Activation: Palladium or tin-palladium catalytic nuclei are deposited on glass surfaces through sensitization and activation chemistry 7
• Electroless Copper Deposition: Autocatalytic reduction of copper ions from solution (typically containing copper sulfate, formaldehyde reducing agent, and complexing agents) deposits 0.5-2.0 µm thick conformal copper seed layers on via sidewalls and surfaces 7
• Electrolytic Copper Fill: Electroplating completes via filling, achieving copper thickness of 10-30 µm with resistivity below 2.0 µΩ·cm 7

Core Seed Layer Architecture:

An alternative approach incorporates a core seed layer as an integral component of the glass core structure, serving as the nucleation site for subsequent conductive layer formation 6. This architecture includes:

• Core Distribution Layer: Electrically conductive traces patterned on glass surfaces and via sidewalls, establishing electrical continuity between first and second surfaces through the via 6
• Material Composition: Copper, nickel, or multi-layer metal stacks (e.g., Ti/Cu/Ti) with total thickness of 0.2-1.0 µm, deposited by sputtering or electroless plating prior to buildup layer formation 6

The core seed layer approach enables simplified processing by eliminating separate via metallization steps, though it requires precise patterning and protection during subsequent buildup layer fabrication 6.

Buildup Layer Integration And Stress Management In Glass Core Packaging Substrates

Buildup layers deposited on glass core surfaces provide fine-pitch routing, component attachment pads, and solder mask definition 128. These layers typically consist of alternating dielectric and conductive layers, with total buildup thickness ranging from 20 µm to 200 µm per side depending on routing complexity 89.

Buildup Layer Material Systems And Processing

Dielectric Materials:

Buildup layer dielectrics are typically photosensitive or non-photosensitive polymer films, including:

• Ajinomoto Build-up Film (ABF): Epoxy-based photosensitive film with Dk ~3.3 at 1 GHz, Df ~0.008, CTE ~40 ppm/°C, widely used for fine-pitch applications 8
• Polyimide Films: High-temperature polymers with Tg >250°C, CTE 20-50 ppm/°C, suitable for applications requiring enhanced thermal stability 8
• Polybenzoxazole (PBO): Low-Dk materials (Dk ~2.8) with excellent planarization and fine-feature resolution 8

Dielectric layers are applied by lamination or spin-coating to thickness of 5-25 µm per layer, followed by photolithographic patterning (for photosensitive materials) or laser via formation (for non-photosensitive materials) to create interconnect openings 8.

Conductive Routing:

Copper routing layers are formed by semi-additive process (SAP) or modified semi-additive process (mSAP):

1. Seed Layer Deposition: Sputtered copper seed layer (0.1-0.3 µm) or electroless copper (0.5-1.0 µm) 8
2. Photoresist Patterning: Dry film or liquid photoresist defines routing patterns with line/space capabilities down to 2 µm/2 µm 9
3. Electrolytic Copper Plating: Copper electroplating fills trenches to 5-15 µm thickness 8
4. Resist Strip and Flash Etch: Photoresist removal and seed layer etching complete pattern transfer 8

Stress Mitigation Strategies For Glass Core Substrates

Compressive stress vectors generated by CTE mismatch between glass cores (CTE ~3-5 ppm/°C) and organic buildup layers (CTE ~40-60 ppm/°C) can induce catastrophic defects including glass fracture, particularly during panel-level processing and thermal excursions 58. Several architectural strategies mitigate these stress concentrations:

Dummy Layer Integration:

Incorporation of dummy layers with reduced CTE relative to standard buildup dielectrics provides stress compensation 8. These dummy layers typically comprise:

• Low-CTE Polymers: Materials such as liquid crystal polymers (LCP) with CTE 15-25 ppm/°C, or filled epoxies with CTE 20-35 ppm/°C 8
• Placement Strategy: Dummy layers positioned as outermost buildup layers or interspersed within buildup stack to balance stress distribution 8
• Thickness Optimization: Dummy layer thickness of 10-50 µm, calibrated through finite element analysis (FEA) to achieve neutral stress state 8

Hybrid Glass-Organic Frame Architecture:

A hybrid substrate design incorporates an organic polymer frame surrounding the glass core, providing mechanical reinforcement at panel edges where stress concentrations are highest 13. This architecture includes:

• Frame Material: Heat-resistant organic polymers such as polyimide or epoxy-based materials with CTE 30-50 ppm/°C, selected for compatibility with legacy toolsets designed for organic substrates 13
• Frame Dimensions: Frame width of 5-20 mm surrounding the glass core perimeter, with thickness matching or slightly exceeding glass core thickness 13
• Bonding Interface: Adhesive bonding or co-lamination integrates the organic frame with the glass core, with interfacial shear strength exceeding 10 MPa to prevent delamination 13

The hybrid architecture protects glass edges from chipping and cracking during handling and processing, while maintaining the electrical and dimensional advantages of the glass core in the active device region 13.

Corner Treatment And Edge Finishing:

Mechanical stress concentrations at substrate corners are mitigated through geometric modifications 1:

• Curved Corners: Radius of curvature between 0.5 mm and 3.0 mm, reducing stress concentration factors by 40-60% compared to sharp corners 1
• Chamfered Edges: 45° chamfers with width 0.3-1.0 mm, providing similar stress reduction benefits 1
• Edge Polishing: Mechanical or chemical-mechanical polishing of glass edges to remove micro-cracks and surface defects that serve as fracture initiation sites 1

Cavity Integration And Embedded Component Technologies In Glass Core Substrates

Advanced 3D packaging architectures increasingly incorporate cavity structures within glass core substrates to accommodate embedded active or passive components, enabling ultra-compact system integration with reduced package height and enhanced electrical performance 310.

Cavity Formation Methods And Geometries

Cavities in glass core substrates are fabricated through controlled material removal processes:

Laser Ablation:

High-power laser systems (typically CO₂ or fiber lasers) remove glass material through localized melting and vaporization, creating cavities with:

• Depth Control: Cavity depths from 50 µm to full glass thickness (through-cavities), controlled by laser power, scan speed, and number of passes 310
• Sidewall Profile: Tapered sidewalls with angles 5-20° from vertical, or near-vertical sidewalls (<5° taper) achievable with optimized laser parameters 3
• Surface Quality: Laser-ablated surfaces exhibit roughness (Ra) of 0.5-2.0 µm, which may require post-processing for applications sensitive to surface topography 3

Mechanical Milling:

CNC milling with diamond-coated tools provides precise cavity formation with:

• Dimensional Accuracy: Cavity dimensions controlled to ±10 µm tolerance 10
• Sidewall Quality: Smooth sidewalls with Ra <0.3 µm, suitable for direct component placement without additional surface treatment 10
• Depth Capability: Cavities from 100 µm to full substrate thickness, with aspect ratios (depth:width) up to 2:1 10

Element Module Integration In Cavity Structures

Cavity portions within glass core substrates accommodate element modules comprising one or more electronic components and associated redistribution circuitry, forming a modularized capsule layer 310. This integration approach includes:

Element Module Architecture:

• Cavity Elements: Active dies (e.g., application processors, memory devices) or passive components (capacitors, inductors) positioned within the cavity accommodation space 310
• Cavity Distribution Layer: Redistribution circuit layer disposed above cavity elements, providing fan-out routing and electrical connection to core vias 3
• Modularization: Multiple cavity elements and their distribution layer are pre-assembled and tested as a discrete module prior to integration into the glass core cavity 3

Assembly Process Flow:

1. Module Preparation: Element modules are fabricated separately, with components attached to a temporary carrier and interconnected through redistribution layers 3
2. Cavity Preparation: Glass core cavities are formed and cleaned, with optional metallization of cavity sidewalls for electrical shielding 3
3. Module Placement: Element modules are positioned in cavity accommodation spaces using pick-and-place equipment with alignment accuracy ±5 µm 3
4. Underfill And Encapsulation: Capillary underfill or molding compound fills gaps between module and cavity walls, providing mechanical support and environmental protection 310

Dimple Structures For Stress Relief:

Concave dimple features are incorporated in molding portions of element packages to accommodate differential thermal expansion and reduce stress concentration at module-cavity interfaces 10. These dimples typically have:

• Geometry: Hemispherical or conical depressions with diameter 100-500 µm and depth 20-100 µm 10
• Distribution: Arranged in regular arrays across the molding surface, with spacing 0.5-2.0 mm 10
• Function: Dimples provide localized compliance, reducing peak interfacial stress by 30-50% during thermal cycling 10

Thermal Management Solutions In Glass Core 3D Packaging Substrates

Effective thermal management is critical for 3D packaging architectures with high power density and vertically stacked dies 2. Glass core substrates enable innovative thermal management approaches leveraging the glass material's thermal properties and structural capabilities.

Glass-Based Cooling Channels For Embedded Die Thermal Management

Through-glass channels oriented parallel to the substrate surface provide direct liquid cooling pathways in proximity to heat-generating components 2. This architecture includes:

Channel Geometry And Formation:

• Channel Dimensions: Width 100-500 µm, height 50-300 µm, length spanning multiple die locations 2
• Fabrication Method: Laser-assisted etching or mechanical milling creates channels in the glass core, with subsequent sealing by buildup layer lamination or glass-to-glass bonding 2
• Channel Density: Multiple parallel channels with pitch 1-5 mm, optimized through computational fluid dynamics (CFD) simulation to balance thermal performance and structural integrity 2

Cooling Fluid Integration:

• Fluid Selection: Deionized water, dielectric fluids (e.g., fluorinated liquids), or two-phase coolants depending on thermal requirements and electrical isolation needs 2
• Flow Rate: Typical flow rates of 10-100 mL/min per channel, providing heat removal capacity of 50-200 W/cm² depending on fluid properties and channel geometry 2
• Manifold Design: Inlet and outlet manifolds integrated at substrate edges or through dedicated via structures, with pressure drop maintained below 50 kPa to minimize pumping power 2

Thermal Performance:

Glass-based cooling channels demonstrate junction-to-fluid thermal resistance of 0.1-0.3 K·cm²/W, enabling die junction temperatures below 85°C for power densities exceeding 100 W/cm² 2. This performance significantly exceeds conventional air-cooled or heat-spreader-based thermal management approaches.

Thermal Via Integration And Heat Spreading Strategies

Thermal vias filled with high-conductivity materials provide vertical heat conduction pathways from embedded dies to external heat sinks