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Glass Core Substrate Board: Advanced Materials And Manufacturing Technologies For Next-Generation Integrated Circuit Packaging

MAR 27, 202656 MINS READ

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Glass core substrate board represents a transformative technology in integrated circuit packaging, leveraging the superior electrical properties, thermal stability, and dimensional precision of glass materials to enable ultra-high-density interconnects and enhanced reliability in semiconductor devices. This advanced substrate architecture addresses critical challenges in miniaturization, signal integrity, and thermal management for high-performance computing, automotive electronics, and telecommunications applications 1,2.
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Fundamental Architecture And Structural Characteristics Of Glass Core Substrate Board

Glass core substrate board technology fundamentally reimagines traditional organic laminate substrates by substituting polymer-based cores with engineered glass materials 1,2. The typical architecture comprises a central glass core layer (ranging from 50 μm to 500 μm thickness) with build-up structures on opposing surfaces 1. These build-up layers consist of alternating dielectric films (typically 10-30 μm per layer) and patterned copper circuitry (5-20 μm thickness), enabling multi-layer routing with line/space dimensions down to 2/2 μm 4.

The glass core itself may be constructed as:

  • Single-piece monolithic glass: A continuous glass substrate with through-glass vias (TGVs) formed by laser drilling, mechanical drilling, or photosensitive glass etching 1,2
  • Multi-layer bonded glass: Two or more discrete glass layers (typically 100-300 μm each) bonded with intermediate adhesive layers (5-15 μm thickness) to achieve desired total thickness and enable complex via structures 10,15
  • Hybrid glass-polymer composite: Glass core surrounded by insulating polymer frames to facilitate handling during manufacturing and reduce edge chipping risks 11,18

The coefficient of thermal expansion (CTE) of borosilicate and aluminosilicate glasses used in these substrates typically ranges from 3.0 to 5.5 ppm/°C (20-260°C), closely matching silicon IC dies (2.6-3.2 ppm/°C) 8,14. This CTE matching minimizes thermomechanical stress during temperature cycling, reducing solder joint fatigue and warpage-induced failures compared to organic substrates with CTE values of 14-18 ppm/°C 3,16.

Material Composition And Properties Of Glass Core Substrate Board

Glass Material Selection And Specification

The glass materials employed in glass core substrate board applications must satisfy stringent requirements for electrical performance, mechanical strength, thermal stability, and processability 6,8. Primary glass compositions include:

  • Borosilicate glass: SiO₂ (70-80 wt%), B₂O₃ (10-15 wt%), Na₂O/K₂O (5-10 wt%), Al₂O₃ (2-5 wt%). Dielectric constant (Dk) = 4.6-5.2 at 1 GHz, dissipation factor (Df) = 0.005-0.008, Young's modulus = 63-70 GPa, thermal conductivity = 1.0-1.2 W/m·K 6,13
  • Aluminosilicate glass: SiO₂ (55-65 wt%), Al₂O₃ (18-25 wt%), MgO/CaO (8-15 wt%), B₂O₃ (3-8 wt%). Dk = 5.8-6.5 at 1 GHz, Df = 0.006-0.010, Young's modulus = 80-90 GPa, enhanced chemical durability 7,17
  • Photosensitive glass: Lithium aluminosilicate with photosensitive additives (Ag, Ce). Enables direct UV patterning and chemical etching for TGV formation with aspect ratios up to 10:1 and via diameters down to 20 μm 5

The surface roughness of glass substrates is typically Ra < 5 nm, enabling ultra-fine-pitch circuitry formation without the "fiber weave effect" that plagues glass-reinforced epoxy laminates 8,11. This atomically smooth surface also facilitates reliable thin-film adhesion and reduces signal loss at high frequencies (>10 GHz) 6,13.

Electrical Performance Characteristics

Glass core substrate board exhibits superior electrical properties critical for high-speed digital and RF applications:

  • Low dielectric constant: Dk values of 4.6-6.5 (1-10 GHz) reduce signal propagation delay by 15-25% compared to FR-4 substrates (Dk = 4.2-4.8 at 1 MHz, but 4.8-5.4 at 1 GHz due to resin relaxation) 6,13
  • Low dissipation factor: Df < 0.010 at frequencies up to 40 GHz minimizes insertion loss in high-speed differential pairs and RF transmission lines 13
  • Frequency-stable properties: Unlike organic dielectrics, glass exhibits minimal Dk and Df variation across temperature (-55°C to +125°C) and frequency (DC to 100 GHz), ensuring predictable impedance control 6
  • High breakdown voltage: Dielectric strength exceeding 20 kV/mm enables aggressive voltage scaling and high-density power delivery networks 7

For advanced applications requiring even lower Dk values, hollow glass fibers filled with low-Dk fluids (air, nitrogen, noble gases) or solid resins can achieve effective Dk values of 2.5-3.5, though manufacturing complexity increases significantly 13.

Mechanical And Thermal Properties

The mechanical robustness of glass core substrate board depends critically on glass composition, thickness, and surface treatment:

  • Flexural strength: 50-150 MPa for pristine glass surfaces; surface treatments (ion exchange, coating) can enhance strength to 200-400 MPa 14,20
  • Fracture toughness: 0.7-0.9 MPa·m^(1/2), requiring careful handling and edge protection strategies 14,18
  • Thermal conductivity: 1.0-1.4 W/m·K, approximately 3-4× higher than organic substrates (0.3-0.4 W/m·K), improving heat dissipation from high-power ICs 6,17
  • Glass transition temperature: Not applicable (glass is already in amorphous state); operational temperature range typically -55°C to +260°C without degradation 8

To mitigate brittleness concerns, several strategies are employed:

  1. Crack prevention layers: Thin polymer coatings (1-5 μm) applied to glass surfaces, with thickness-to-core ratios of 0.0001-0.05, absorb mechanical stress and arrest crack propagation 20
  2. Laser-treated edges: Controlled laser processing creates compressive stress zones and modified nanoporosity at substrate edges, reducing singulation-induced microcracking 14
  3. Polymer frame reinforcement: Surrounding glass cores with epoxy or polyimide frames during processing provides mechanical support and reduces handling damage 11,18

Manufacturing Processes For Glass Core Substrate Board

Through-Glass Via (TGV) Formation Technologies

TGV fabrication represents the most critical and challenging process step in glass core substrate board manufacturing 1,2,7. Multiple approaches exist, each with distinct advantages and limitations:

Laser Drilling

  • CO₂ laser ablation: Wavelength 10.6 μm, pulse duration 10-100 ns, repetition rate 10-100 kHz. Achieves via diameters of 50-200 μm with aspect ratios up to 5:1. Thermal damage zone extends 5-15 μm from via wall, requiring post-processing cleanup 14
  • UV laser drilling: Wavelength 355 nm (Nd:YAG third harmonic), pulse duration 10-30 ns. Enables smaller via diameters (30-100 μm) with reduced thermal damage (<5 μm), but slower processing speed (0.5-2 seconds per via) 14
  • Femtosecond laser processing: Pulse duration <500 fs, enables "cold ablation" with minimal heat-affected zone (<1 μm) and via diameters down to 10 μm, but requires expensive equipment and precise beam control 14

Mechanical Drilling

  • Carbide or diamond-coated drill bits (diameter 100-500 μm) achieve high throughput (>1000 vias/minute) but generate significant edge chipping (10-30 μm) and microcracking 7
  • Ultrasonic-assisted drilling reduces chipping to 5-15 μm and extends tool life by 2-3× 7

Photosensitive Glass Etching

  • UV exposure (wavelength 280-320 nm, dose 1-10 J/cm²) followed by thermal treatment (500-600°C, 1-2 hours) and chemical etching (10% HF solution, 20-60 minutes) creates high-aspect-ratio vias (up to 10:1) with excellent sidewall smoothness (Ra < 50 nm) 5
  • Enables simultaneous formation of thousands of vias with precise dimensional control (±2 μm tolerance) 5

Via Metallization And Conductor Formation

After TGV formation, metallization establishes electrical connectivity through the glass core 1,2,8,12:

Electroless Plating Seed Layer

  1. Surface activation: Palladium chloride (PdCl₂) solution treatment (0.1-0.5 g/L, pH 2-4, 40-60°C, 5-15 minutes) deposits catalytic Pd nanoparticles on glass surfaces 8,12
  2. Electroless nickel plating: Nickel sulfate (20-30 g/L), sodium hypophosphite reducer (20-30 g/L), pH 4.5-5.5, temperature 80-90°C, deposition rate 5-15 μm/hour. Critical parameter: phosphorus content must be <5 wt% to minimize residual stress and prevent cracking 8,12
  3. Electroless copper plating: Copper sulfate (8-12 g/L), formaldehyde reducer (2-5 mL/L), EDTA complexing agent (30-50 g/L), pH 12.5-13.0, temperature 60-70°C, deposition rate 2-5 μm/hour 8

Electrolytic Copper Plating

  • Acid copper sulfate bath: CuSO₄·5H₂O (200-250 g/L), H₂SO₄ (50-80 g/L), chloride ions (40-80 ppm), organic additives (brightener, leveler, suppressor) 8,12
  • Current density: 1-4 A/dm² for via filling, 0.5-2 A/dm² for surface circuitry
  • Plating thickness: 15-40 μm for TGV filling (depending on via diameter), 5-18 μm for surface traces 1,2

Via Filling Optimization To prevent void formation during electrolytic plating of high-aspect-ratio TGVs, via geometry must satisfy empirical relationships 7:

Expression (1): 0.020 < (D-d)ν/(2h)
Expression (2): 3.7 > h/(D*ν)

Where D = via diameter at entry surface (μm), d = via diameter at exit surface (μm), h = glass thickness (μm), ν = plating solution viscosity (cP). Tapered via profiles (D > d) facilitate air bubble escape and ensure complete filling 7.

Build-Up Layer Fabrication

Following core metallization, dielectric build-up layers and fine-pitch circuitry are formed using sequential lamination and patterning 1,2,4:

  1. Dielectric lamination: Photosensitive or thermosetting dielectric films (epoxy, polyimide, benzocyclobutene) are laminated at 80-120°C, 0.2-0.5 MPa pressure, then cured at 150-250°C for 30-90 minutes 4
  2. Via formation in dielectrics: Laser ablation (CO₂ or UV) or photolithographic patterning creates microvias (diameter 25-75 μm) connecting build-up layers 4
  3. Circuit patterning: Semi-additive process (SAP) or modified semi-additive process (mSAP) enables line/space dimensions of 2/2 μm to 10/10 μm 4
  4. Surface finish: Electroless nickel/immersion gold (ENIG), organic solderability preservative (OSP), or immersion silver applied to final layer pads 4

Multi-Layer Glass Core Bonding

For applications requiring thicker substrates or complex internal structures, multiple glass layers are bonded together 10,15,19:

Adhesive Bonding

  • Thermoplastic or thermosetting polymer adhesives (thickness 5-20 μm) applied by spin coating or lamination 10,15
  • Bonding conditions: Temperature 150-200°C, pressure 0.5-2.0 MPa, time 30-120 minutes under vacuum (<100 Pa) to prevent void formation 15,19
  • Adhesive materials: Epoxy resins (Tg 150-180°C), polyimides (Tg 250-350°C), or benzocyclobutene (BCB, Tg 350°C) 10

Anodic Bonding

  • Direct glass-to-glass bonding at 300-450°C under applied voltage (200-1000 V) creates hermetic seal without intermediate adhesive layer 10
  • Requires matched CTE between glass layers (ΔCTE < 0.5 ppm/°C) to prevent delamination during thermal cycling 10

Optical Contact Bonding

  • Ultra-smooth glass surfaces (Ra < 1 nm) brought into intimate contact form van der Waals bonds, then strengthened by thermal annealing at 400-600°C 10
  • Achieves bond strength >10 MPa without adhesives, but requires extremely precise surface preparation 10

Applications Of Glass Core Substrate Board In Advanced Electronics

High-Performance Computing And Data Center Applications

Glass core substrate board technology addresses critical bottlenecks in next-generation processors and accelerators 1,2,4:

Multi-Die Integration Platforms

  • Enables 2.5D and 3D heterogeneous integration of logic dies, memory stacks (HBM), and I/O chiplets on a single substrate with ultra-short interconnects (<500 μm) 16
  • Silicon bridge interposers embedded in glass core cavities provide high-density die-to-die connections (pitch 40-55 μm) while glass core handles power delivery and global routing 16
  • Reduces package warpage to <50 μm (vs. 150-300 μm for organic substrates) across 60×60 mm² footprints, enabling reliable solder joint formation for >10,000 I/O connections 3,16

High-Speed Serial Links

  • Low Dk and Df enable 112 Gbps PAM-4 signaling with insertion loss <1.5 dB at 56 GHz Nyquist frequency over 50 mm trace length 6,13
  • Reduced signal skew (<5 ps across 100 mm differential pair) due to absence of fiber weave effect and stable dielectric properties 13
  • Supports PCIe Gen6 (64 GT/s), DDR5 (6400 MT/s), and emerging standards with 30-50% margin improvement vs. organic substrates 6

Thermal Management

  • 3-4× higher thermal conductivity than organic substrates enables direct heat spreading from high-power dies (TDP >300 W) 6,17
  • Integration of copper or aluminum heat spreaders directly onto glass core (bonded at 200-250°C) creates efficient thermal pathways 5
  • Embedded thermal vias (diameter 200-500 μm, pitch 1-2 mm) filled with high-conductivity materials (copper, silver-filled epoxy) further enhance heat dissipation 5

Automotive Electronics And Harsh Environment Applications

The superior thermal stability and mechanical reliability of glass core substrate board make it ideal for automotive and industrial applications 3,8,17:

Powertrain And Safety Systems

  • Operational temperature range -55°C to +175°C (with appropriate dielectric materials) meets AEC-Q100 Grade 0
OrgApplication ScenariosProduct/ProjectTechnical Outcomes
Intel CorporationHigh-performance computing platforms requiring 2.5D/3D heterogeneous integration of logic dies, HBM memory stacks, and I/O chiplets with ultra-short interconnects and reliable solder joints for advanced processors and accelerators.Glass Core Substrate TechnologyEnables ultra-high-density interconnects with build-up structures on glass cores, supporting multi-die integration with CTE matching silicon (3.0-5.5 ppm/°C vs 2.6-3.2 ppm/°C for Si), reducing package warpage to <50 μm across 60×60 mm² footprints for >10,000 I/O connections.
Toppan Inc.High-density semiconductor packaging requiring void-free via filling in glass substrates with aspect ratios up to 10:1, suitable for advanced IC devices demanding ultra-fine pitch interconnects and enhanced reliability.Glass Core Multilayer Wiring BoardOptimized through-glass via geometry satisfying 0.020<(D-d)ν/(2h) and 3.7>h/(D*ν) prevents void formation during electrolytic plating, with electroless nickel plating containing <5 mass% phosphorus to minimize residual stress and cracking.
Samsung Electronics Co. Ltd.Advanced semiconductor packages requiring high-density die-to-die connections (pitch 40-55 μm) for multi-chip modules in data center applications, AI accelerators, and high-performance computing systems.Glass Core Substrate with Si Bridge InterposerMinimizes silicon interposer size while maintaining chip-to-chip connectivity by embedding Si bridge in glass core cavity, reducing package warpage and enabling miniaturization with multi-layer wiring under glass core substrate.
Schott AGHigh-speed telecommunications and data center interconnects requiring optical signal transmission combined with electrical routing, suitable for photonic integrated circuits and optical computing applications operating above 10 GHz.Glass Circuit Board with Optical FunctionalitiesIntegrates optical waveguides within glass substrate providing low thermal mismatch with semiconductor dies, enabling both electrical and optical signal transmission with superior thermal stability and dimensional precision.
LG Innotek Co. Ltd.Compact semiconductor packages for automotive electronics and mobile devices requiring enhanced reliability under thermal cycling (-55°C to +175°C) and mechanical stress, with improved signal integrity for high-speed applications.Glass Core Circuit Board with Insulating SubstrateSuppresses warpage and breakage through controlled spacing between glass core layer and separate insulating substrate with connection build-up layers, reducing electrical resistance and delay rates while enhancing mechanical strength and preventing crack propagation.
Reference
  • Glass core substrate for integrated circuit devices and methods of making the same
    PatentWO2011084235A2
    View detail
  • Glass core substrate for integrated circuit devices and methods of making the same
    PatentActiveUS20120192413A1
    View detail
  • Circuit board and semiconductor package comprising same
    PatentWO2025206899A1
    View detail
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