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Glass Core Substrate Panel: Advanced Materials Engineering For High-Performance Integrated Circuit Packaging

MAR 27, 202665 MINS READ

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Glass core substrate panels represent a transformative shift in semiconductor packaging technology, offering superior electrical performance, thermal stability, and dimensional precision compared to traditional organic core materials. These substrates integrate ultra-thin glass layers (typically 50–300 μm) as the structural foundation for multi-layer wiring architectures, enabling high-density through-glass vias (TGVs) and enhanced signal integrity for advanced integrated circuit (IC) devices 3. The adoption of glass core substrate panels addresses critical challenges in next-generation packaging, including coefficient of thermal expansion (CTE) mismatch, warpage control, and the demand for finer feature sizes in heterogeneous integration applications 2.
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Molecular Composition And Structural Characteristics Of Glass Core Substrate Panels

Glass core substrate panels employ specialized glass compositions engineered to balance mechanical robustness, thermal compatibility, and electrical insulation properties. The most prevalent glass types include alkali-free borosilicate and aluminosilicate glasses, which exhibit dielectric constants (Dk) in the range of 4.5–6.5 at 1 GHz and dissipation factors (Df) below 0.005 3. These compositions are deliberately formulated to minimize alkali ion migration, a critical requirement for preventing contamination of adjacent semiconductor layers during high-temperature processing (typically 250–400°C) 11.

The structural architecture of a glass core substrate panel comprises three primary elements: the glass core layer, through-glass vias (TGVs) for vertical electrical interconnection, and build-up layers on both surfaces 4. The glass core thickness typically ranges from 100 μm to 500 μm, with thinner cores (50–100 μm) increasingly adopted for ultra-compact packaging solutions 7. TGVs are formed through laser drilling or wet chemical etching, followed by metallization with copper or nickel/copper composite structures 6. The via diameter ranges from 20 μm to 100 μm, with aspect ratios (depth-to-diameter) of 3:1 to 10:1 achievable depending on the fabrication method 3.

Key material properties include:

  • Coefficient of Thermal Expansion (CTE): Glass cores exhibit CTE values of 3.0–4.5 ppm/°C, closely matching silicon (2.6 ppm/°C) and significantly lower than organic laminates (14–18 ppm/°C), thereby reducing thermomechanical stress during thermal cycling 8.
  • Young's Modulus: Glass cores provide stiffness values of 70–90 GPa, approximately 10× higher than organic cores (5–8 GPa), which enhances panel flatness and reduces warpage during processing 13.
  • Dielectric Strength: Breakdown voltages exceed 10 kV/mm, ensuring reliable electrical isolation in high-voltage applications 3.
  • Surface Roughness: As-formed glass surfaces exhibit Ra values below 1 nm, enabling superior lithographic resolution for fine-pitch redistribution layers (RDLs) 2.

The glass core may consist of a single monolithic layer or a multi-layer laminate structure. Multi-layer glass cores, formed by bonding two or more discrete glass sheets with intermediate adhesive or fusion bonding layers, offer enhanced design flexibility for embedding passive components or creating internal cavity structures 10. The bonding layer materials include low-temperature glass frits, polymer adhesives, or direct fusion bonding achieved through surface activation and thermal compression at 400–600°C 10.

Precursors And Synthesis Routes For Glass Core Substrate Panel Fabrication

The manufacturing of glass core substrate panels involves a multi-stage process integrating glass preparation, via formation, metallization, and build-up layer construction. The process flow begins with the selection and preparation of ultra-flat glass sheets, typically sourced from specialized glass manufacturers employing float glass or fusion draw processes to achieve thickness uniformity within ±5 μm across panel dimensions of 510 mm × 515 mm or larger 7.

Glass Core Preparation And Surface Treatment

Raw glass panels undergo rigorous cleaning and surface treatment to enhance adhesion with subsequent metallization layers. Chemical functionalization techniques include:

  • Silane Coupling Agents: Application of aminosilanes or epoxysilanes to create reactive surface groups that bond covalently with organic dielectric materials, improving interfacial adhesion strength to >15 MPa in peel tests 16.
  • Plasma Activation: Oxygen or argon plasma treatment to increase surface energy (from ~40 mN/m to >60 mN/m) and create hydroxyl-rich surfaces for improved wettability 16.
  • Edge Profiling: Mechanical or laser-based edge chamfering to increase edge surface area by 20–40% and reduce stress concentration points, thereby mitigating edge chipping during handling 16.

Through-Glass Via (TGV) Formation

TGV fabrication represents the most critical and technically challenging step, with two dominant approaches:

Laser Drilling: Ultrafast picosecond or femtosecond lasers ablate glass material through multi-pass scanning, creating vias with diameters of 30–100 μm and taper angles <5°. Process parameters include pulse energy of 10–50 μJ, repetition rates of 100–500 kHz, and scanning speeds of 100–500 mm/s 8. Post-drilling cleaning with HF-based solutions removes recast layers and micro-cracks.

Wet Chemical Etching: Photosensitive glass compositions (e.g., Foturan®) are exposed to UV light through a photomask, then thermally developed at 500–600°C to create crystalline regions. Subsequent immersion in 10% HF solution selectively etches the crystallized zones at rates of 10–30 μm/min, forming vias with vertical sidewalls and diameters down to 20 μm 3.

Metallization And Conductor Pattern Formation

Following via formation, metallization establishes electrical conductivity through the glass core and on surface layers:

  • Electroless Nickel Plating: A thin nickel seed layer (0.5–2 μm) is deposited via electroless plating using nickel sulfate baths at 80–90°C, with phosphorus content controlled to ≤5 mass% to minimize internal stress and reduce cracking susceptibility 6.
  • Electrolytic Copper Plating: Copper is electrodeposited to fill TGVs and form surface conductor patterns, with typical thicknesses of 10–30 μm. Plating baths operate at current densities of 1–5 A/dm² and temperatures of 25–35°C, using additives to control grain structure and minimize voids 6.
  • Pattern Etching: Photolithographic patterning followed by wet or dry etching defines conductor traces with line widths down to 5 μm and spacing of 5 μm, enabling high-density interconnect (HDI) routing 3.

Build-Up Layer Construction

Alternating layers of organic dielectric materials (e.g., epoxy-based prepregs, polyimides, or benzocyclobutene) and copper redistribution layers are sequentially laminated and patterned on both sides of the glass core. Each build-up layer undergoes:

  • Lamination: Vacuum lamination at 180–220°C and pressures of 2–5 MPa to ensure void-free adhesion 4.
  • Via Formation: Laser drilling or photolithography to create microvias (25–75 μm diameter) connecting adjacent metal layers 4.
  • Metallization: Copper plating to fill microvias and form RDL patterns with thicknesses of 5–15 μm 4.

Typical build-up structures comprise 2–6 layers per side, achieving total substrate thicknesses of 300–800 μm 3.

Performance Characteristics And Reliability Metrics Of Glass Core Substrate Panels

Glass core substrate panels deliver measurable performance advantages across electrical, thermal, and mechanical domains, validated through extensive characterization and reliability testing.

Electrical Performance

  • Signal Integrity: The low Dk (4.5–6.5) and ultra-low Df (<0.005) of glass cores minimize signal attenuation and crosstalk, enabling data transmission rates exceeding 56 Gbps per lane with insertion loss <1 dB/cm at 28 GHz 3.
  • Power Delivery: Low resistivity copper conductors (1.7–2.0 μΩ·cm) in TGVs and RDLs support high current densities (>10 A/mm²) with minimal voltage drop, critical for power-hungry AI accelerators and high-performance computing (HPC) processors 3.
  • Impedance Control: Tight dimensional tolerances (±3 μm) and uniform dielectric thickness enable controlled impedance traces (50 Ω ±5%) for high-speed differential signaling 2.

Thermal Management

  • Thermal Conductivity: Glass cores exhibit thermal conductivity of 1.0–1.4 W/m·K, lower than silicon (150 W/m·K) but sufficient for moderate heat dissipation when combined with thermal vias and heat spreaders 8.
  • CTE Matching: The near-silicon CTE of glass (3.0–4.5 ppm/°C) reduces interfacial stress between the substrate and silicon dies, minimizing solder joint fatigue and die cracking during thermal cycling (−40°C to +125°C, 1000 cycles) 8.
  • Thermal Stability: Glass cores maintain dimensional stability and electrical properties up to 400°C, enabling compatibility with high-temperature assembly processes such as die attach and solder reflow 11.

Mechanical Robustness

  • Flexural Strength: Glass core substrates exhibit three-point bending strengths of 150–250 MPa, adequate for handling and assembly when panel thickness exceeds 200 μm 12.
  • Warpage Control: The high modulus of glass (70–90 GPa) limits panel warpage to <50 μm across 510 mm × 515 mm panels, even after multiple thermal excursions, ensuring compatibility with automated pick-and-place equipment 13.
  • Edge Strength: Edge profiling and chemical strengthening treatments increase edge fracture toughness by 30–50%, reducing yield losses from edge chipping during dicing and handling 16.

Reliability And Failure Mechanisms

Accelerated reliability testing protocols validate glass core substrate panels for demanding applications:

  • Temperature Cycling: Substrates survive >1000 cycles (−40°C to +125°C, 15 min dwell) without delamination or conductor cracking, as verified by cross-sectional scanning electron microscopy (SEM) and electrical continuity testing 8.
  • Moisture Resistance: Exposure to 85°C/85% RH for 1000 hours results in <1% change in dielectric constant and no measurable degradation in insulation resistance (>10¹² Ω) 3.
  • Mechanical Shock: Drop tests (1.5 m height, 1500 G peak acceleration) confirm solder joint integrity and absence of glass fracture when substrate thickness ≥300 μm 8.

Critical failure modes include:

  • Glass Cracking: Induced by excessive compressive stress from build-up layers or mishandling; mitigated through stress-relief features (e.g., polymer frames, edge profiling) and optimized layer stack design 13.
  • TGV Voiding: Incomplete copper filling during electroplating leads to electrical opens; addressed by optimized plating chemistry and pulse-reverse current waveforms 6.
  • Delamination: Interfacial failure between glass and organic layers due to inadequate surface treatment; prevented by silane coupling and plasma activation 16.

Applications Of Glass Core Substrate Panels In Advanced Packaging Architectures

Glass core substrate panels enable a diverse range of high-performance packaging solutions across computing, communications, and automotive sectors.

High-Performance Computing (HPC) And Artificial Intelligence (AI) Accelerators

Glass core substrates are increasingly adopted for 2.5D and 3D heterogeneous integration platforms, where multiple chiplets (CPU, GPU, memory, I/O) are co-packaged on a single interposer or substrate. The superior electrical properties of glass enable:

  • High-Bandwidth Memory (HBM) Integration: Glass interposers support >10,000 microbumps per die with pitches of 40–55 μm, facilitating HBM stacks with aggregate bandwidths exceeding 1 TB/s 3.
  • Chiplet-to-Chiplet Communication: Low-loss signal routing at 56 Gbps enables die-to-die interconnects with latencies <1 ns and power consumption <1 pJ/bit, critical for disaggregated processor architectures 2.
  • Thermal Management: Embedded thermal vias and integration with vapor chambers or heat sinks dissipate >500 W from multi-die packages, maintaining junction temperatures below 85°C under full load 8.

Representative implementations include Intel's EMIB (Embedded Multi-die Interconnect Bridge) and AMD's Infinity Fabric, both leveraging glass or glass-like substrates for high-density interconnects 2.

Radio Frequency (RF) And Millimeter-Wave (mmWave) Modules

The low Df of glass cores (<0.005 at 28 GHz) makes them ideal for 5G/6G RF front-end modules and phased-array antennas:

  • Antenna-in-Package (AiP): Glass substrates host integrated patch antennas and beamforming ICs, achieving radiation efficiencies >70% and gain >10 dBi at 28 GHz 3.
  • Low Insertion Loss: Signal traces on glass exhibit insertion loss <0.5 dB/cm at 77 GHz, enabling automotive radar modules with detection ranges >300 m 3.
  • Hermetic Sealing: Glass-to-glass or glass-to-metal sealing techniques create hermetic cavities for sensitive RF components, ensuring long-term reliability in harsh environments 10.

Automotive Electronics And Power Modules

Glass core substrates address the stringent reliability and thermal requirements of automotive applications:

  • Power Semiconductor Packaging: Glass substrates with thick copper layers (50–100 μm) and embedded cooling channels support SiC and GaN power devices operating at 200°C junction temperatures and switching frequencies >100 kHz 8.
  • Sensor Fusion Modules: Glass interposers integrate LiDAR, radar, and camera processing ICs with low latency (<10 ms) and high reliability (AEC-Q100 Grade 1 qualified) 8.
  • Thermal Cycling Endurance: Automotive-grade glass substrates survive >3000 cycles (−40°C to +150°C) without solder joint failure, meeting ISO 16750 standards 8.

Display And Optoelectronic Devices

Glass core substrates serve as the foundation for advanced display technologies:

  • Micro-LED Displays: Ultra-flat glass substrates (Ra <1 nm) enable precise alignment and bonding of micro-LED dies with pitches <10 μm, achieving pixel densities >2000 ppi 11.
  • Flexible OLED Panels: Thin glass cores (50–100 μm) laminated with flexible polymer layers provide mechanical support while maintaining optical transparency (>90% transmittance at 550 nm) 11.
  • Photonic Integrated Circuits (PICs): Glass substrates with embedded waveguides and optical vias facilitate co-packaging of lasers, modulators, and photodetectors for data center interconnects operating at 400 Gbps and beyond 3.

Stress Mitigation And Hybrid Panel Architectures For Enhanced Manufacturability

The inherent brittleness of glass poses significant challenges for large-panel processing, necessitating innovative design strategies to improve handling robustness and yield.

Hybrid Glass-Organic Panel Designs

Hybrid substrates combine a central glass core with a peripheral organic polymer frame, leveraging the strengths of both materials 2. The organic frame, typically 10–20 mm wide and composed of epoxy-based laminates or polyimide, provides:

  • Edge Protection: The polymer frame absorbs impact energy during handling, reducing edge chipping by >80% compared to bare glass panels 2.
  • Tooling Compatibility: The frame enables processing on legacy equipment designed for organic substrates, eliminating the need for specialized glass-handling toolsets and reducing capital expenditure 7.
  • Stress Buffering: The compliant polymer frame accommodates differential thermal expansion between the glass core and build-up layers, reducing compressive stress in the glass by 30–50% 13.

Fabrication of hybrid panels involves:

  1. Frame Attachment: Pre-formed polymer frames are adhesively bonded to the glass core perimeter using epoxy or acrylic adhesives cured at 150–180°C 2.
  2. Co-Processing: The hybrid panel undergoes standard build-up layer lamination, drilling, and metallization processes 2.
OrgApplication ScenariosProduct/ProjectTechnical Outcomes
Intel CorporationHigh-performance computing and AI accelerators requiring heterogeneous integration with multiple chiplets, HBM integration with >10,000 microbumps per die, and chiplet-to-chiplet communication at 56 Gbps.EMIB (Embedded Multi-die Interconnect Bridge)Hybrid glass-organic substrate design reduces edge chipping by >80% and enables processing on legacy toolsets, with CTE matching silicon (3.0-4.5 ppm/°C) to minimize thermomechanical stress during thermal cycling.
Intel CorporationAdvanced IC packaging for 2.5D/3D integration, RF and millimeter-wave modules for 5G/6G applications, and automotive power semiconductor packaging operating at 200°C junction temperatures.Glass Core Package SubstrateThrough-glass vias (TGVs) with 20-100 μm diameter enable high-density vertical interconnection, low dielectric constant (4.5-6.5) and dissipation factor (<0.005) support data transmission >56 Gbps with insertion loss <1 dB/cm at 28 GHz.
Intel CorporationLarge-panel processing (510mm × 515mm) for semiconductor packaging requiring compatibility with legacy organic substrate toolsets and enhanced handling robustness in high-volume manufacturing environments.Glass Core Hybrid PanelEdge profiling and chemical functionalization with silane coupling agents improve interfacial adhesion strength to >15 MPa, organic polymer frame provides edge protection and stress buffering reducing compressive stress by 30-50%.
Samsung Electronics Co. Ltd.Multi-chip semiconductor packages requiring miniaturization and multi-functionalization with at least two stacked semiconductor devices, suitable for advanced heterogeneous integration applications.Glass Core Substrate with Si Bridge InterposerGlass core substrate with embedded silicon bridge interposer in central cavity enables chip-to-chip connection while minimizing warpage, maintaining dimensional stability with Young's modulus of 70-90 GPa.
Toppan Printing Co. Ltd.Multi-layer wiring substrates for semiconductor packages requiring reliable electrical interconnection through glass cores with enhanced mechanical robustness and thermal cycling endurance (>1000 cycles -40°C to +125°C).Glass Core Multi-layer Wiring SubstrateElectroless nickel plating layer with phosphorus content ≤5 mass% on glass core reduces cracking susceptibility, copper plating layer provides conductor pattern with controlled impedance (50Ω ±5%) for high-speed signaling.
Reference
  • Substrate strip, substrate panel, and manufacturing method of substrate strip
    PatentActiveTW201601603A
    View detail
  • Hybrid glass and organic substrates
    PatentPendingUS20260005081A1
    View detail
  • Glass core substrate for integrated circuit devices and methods of making the same
    PatentActiveUS20160284637A1
    View detail
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