Glass Core Substrate Sheet: Advanced Materials And Manufacturing Technologies For High-Density Integrated Circuit Packaging

Structural Composition And Material Architecture Of Glass Core Substrate Sheets

Glass core substrate sheets comprise multi-layered architectures designed to integrate electrical functionality with mechanical robustness. The fundamental structure consists of a glass core layer—typically ranging from 50 μm to 500 μm in thickness—sandwiched between build-up layers that provide routing capabilities and component attachment interfaces 12. The glass core itself may be constructed from a single monolithic glass piece or multiple discrete glass sections bonded together using specialized adhesive interlayers 410.

The material selection for the glass core prioritizes compositions with CTE values between 3.0–7.5 ppm/°C to minimize thermal mismatch with silicon dies (CTE ~2.6 ppm/°C) 13. Common glass types include borosilicate, aluminosilicate, and alkali-free display glasses, each offering distinct trade-offs between processability, cost, and performance 614. The dielectric constant (Dk) of these glasses typically ranges from 4.5 to 6.5 at 1 GHz, significantly lower than conventional FR-4 organic substrates (Dk ~4.2–4.8), enabling reduced signal propagation delays and crosstalk in high-frequency applications 25.

Build-up structures on both sides of the glass core consist of alternating dielectric and metallization layers, typically comprising:

• Adhesive/dielectric layers: Polar group-containing alicyclic olefin polymers or epoxy-based resins with thickness ranging 10–50 μm per layer, providing electrical insulation and mechanical bonding 811
• Copper redistribution layers: Electroplated copper traces with line width/spacing capabilities down to 2/2 μm, enabling ultra-fine-pitch interconnects 17
• Surface treatment layers: Silane coupling agents or nickel plating (phosphorus content ≤5 mass%) applied to glass surfaces to enhance adhesion with organic dielectrics and prevent delamination 78

Through-glass vias (TGVs) provide vertical electrical connectivity, with diameters typically ranging from 20 μm to 200 μm and aspect ratios up to 10:1 15. These vias are filled with conductive materials—primarily electroplated copper, though some designs incorporate nickel barrier layers to prevent copper diffusion into the glass matrix 710.

Manufacturing Processes And Fabrication Techniques For Glass Core Substrate Sheets

Via Formation And Metallization Methods

The creation of through-glass vias represents one of the most critical and challenging steps in glass core substrate sheet fabrication. Multiple techniques have been developed to address the brittleness of glass while achieving the required via density and dimensional precision:

Laser drilling remains the dominant method for TGV formation, utilizing ultraviolet (UV) or infrared (IR) laser systems with pulse durations in the picosecond to femtosecond range 517. The laser ablation process creates controlled nanoporosity gradients in the glass, with laser-treated areas exhibiting higher nanoporosity than untreated regions—a characteristic that facilitates subsequent metallization and reduces crack propagation during thermal cycling 5. Typical laser drilling parameters include:

• Wavelength: 355 nm (UV) or 1064 nm (IR)
• Pulse energy: 10–100 μJ
• Repetition rate: 10–500 kHz
• Drilling speed: 50–200 vias per second for 50 μm diameter holes 5

Wet chemical etching using hydrofluoric acid (HF) solutions provides an alternative approach for creating TGVs, particularly for larger via diameters (>100 μm) 17. This method requires photolithographic masking and typically achieves etch rates of 1–5 μm/min depending on glass composition and HF concentration (typically 5–20% by volume). However, wet etching produces tapered via profiles and requires careful control to prevent over-etching and dimensional variation 417.

Mechanical drilling using diamond-coated or carbide drill bits remains viable for low-density applications or prototyping, though it introduces higher risk of micro-cracking and edge chipping compared to laser methods 10.

Following via formation, metallization proceeds through a multi-step electroless and electrolytic plating sequence 17:

1. Surface activation: Palladium or tin-palladium catalytic seeding of via walls (immersion time 2–10 minutes at 40–60°C)
2. Electroless nickel plating: Deposition of 0.5–2.0 μm nickel barrier layer with controlled phosphorus content (≤5 mass%) to minimize internal stress and cracking susceptibility 7
3. Electroless copper plating: Thin copper seed layer (0.1–0.5 μm) to enable subsequent electrolytic deposition
4. Electrolytic copper plating: Bulk copper fill to via depth plus 5–15 μm overburden, using acid copper sulfate baths at current densities of 1–5 A/dm² 17
5. Chemical-mechanical polishing (CMP): Planarization to remove overburden and achieve co-planarity within ±2 μm 2

Multi-Layer Glass Core Assembly And Bonding

For applications requiring enhanced mechanical strength or specialized electrical properties, multi-layer glass core structures are fabricated by bonding two or more discrete glass sheets 410. The bonding process employs several approaches:

Adhesive bonding utilizes thermosetting polymers (typically epoxy or polyimide-based) applied as thin films (5–25 μm thickness) between glass layers 410. The assembly undergoes vacuum lamination at temperatures of 150–200°C and pressures of 0.5–3.0 MPa for 30–90 minutes to achieve void-free bonding. Critical parameters include:

• Glass surface roughness: Ra < 10 nm to ensure uniform adhesive wetting
• Adhesive viscosity: 1,000–10,000 cP at application temperature
• CTE matching: Adhesive CTE should fall between glass and copper (typically 15–25 ppm/°C) to minimize interfacial stress 4

Direct glass-to-glass bonding (fusion bonding) eliminates organic interlayers by creating covalent Si-O-Si bonds at the interface through high-temperature (>600°C) annealing in controlled atmospheres 10. This approach provides superior thermal stability and dimensional precision but requires extremely flat and clean glass surfaces (surface energy >50 mN/m).

Each glass layer in a multi-layer stack may contain pre-formed TGVs that align during bonding to create continuous vertical interconnects 410. Alignment tolerances of ±5 μm are typically required, necessitating precision fixturing and optical alignment systems during assembly.

Build-Up Layer Formation And Patterning

Following core fabrication, build-up layers are sequentially deposited and patterned on both sides of the glass core using processes adapted from conventional PCB manufacturing 123:

1. Dielectric layer application: Spin coating, spray coating, or lamination of photosensitive or non-photosensitive dielectric films
2. Via formation in dielectric: Laser ablation or photolithographic patterning to create microvias connecting to underlying copper features
3. Desmear and surface preparation: Plasma treatment or chemical desmear to remove resin residue and enhance copper adhesion
4. Copper metallization: Semi-additive process (SAP) or modified semi-additive process (mSAP) to form fine-pitch redistribution layers
5. Solder mask application: Screen printing or photoimageable solder mask with openings for component attachment pads

This build-up sequence is repeated 2–6 times per side to achieve the required routing density and layer count 13.

Electrical And Thermal Performance Characteristics Of Glass Core Substrate Sheets

Dielectric Properties And Signal Integrity

Glass core substrate sheets exhibit exceptional electrical properties that directly translate to improved signal integrity in high-speed digital and RF applications. Key dielectric parameters include:

• Dielectric constant (Dk): 4.5–6.5 at 1 GHz, with minimal frequency dependence up to 40 GHz 26
• Dissipation factor (Df): 0.002–0.008 at 1 GHz, significantly lower than organic substrates (Df ~0.015–0.025) 15
• Dielectric breakdown strength: 20–40 kV/mm, providing robust insulation for high-voltage applications 614
• Volume resistivity: >10¹⁴ Ω·cm, ensuring negligible leakage current 2

These properties enable several performance advantages:

Reduced signal attenuation: The low Df of glass cores minimizes dielectric losses in transmission lines, with insertion loss typically 20–30% lower than FR-4 substrates at 10 GHz 15. For a 50 Ω microstrip line on a 100 μm thick glass core, measured insertion loss is approximately 0.8 dB/cm at 10 GHz compared to 1.2 dB/cm for equivalent FR-4 designs 2.

Enhanced impedance control: The uniform Dk and minimal moisture absorption (<0.1% by weight) of glass provide stable characteristic impedance across environmental conditions 614. Impedance variation is typically held within ±5% over temperature ranges of -40°C to +125°C and humidity conditions up to 85% RH 1.

Reduced crosstalk: Lower Dk values decrease capacitive coupling between adjacent signal traces, with near-end crosstalk typically 3–5 dB lower than organic substrates for equivalent trace geometries 5.

Thermal Management And CTE Matching

The thermal properties of glass core substrate sheets address critical challenges in advanced IC packaging:

Coefficient of thermal expansion: Glass cores with CTE values of 3.0–7.5 ppm/°C provide excellent matching to silicon dies (CTE ~2.6 ppm/°C), dramatically reducing thermomechanical stress during temperature cycling 136. This CTE matching minimizes solder joint fatigue and die cracking, with reliability testing demonstrating >2,000 thermal cycles (-40°C to +125°C) without failure for flip-chip assemblies on glass core substrates 23.

In contrast, organic substrates exhibit in-plane CTE of 12–17 ppm/°C, creating significant CTE mismatch that limits die size and interconnect pitch 1. For large die (>20 mm × 20 mm) and fine-pitch interconnects (<100 μm pitch), glass core substrates enable reliable assembly that would be impractical with organic alternatives 35.

Thermal conductivity: Standard glass compositions exhibit thermal conductivity of 1.0–1.4 W/(m·K), comparable to organic substrates but lower than ceramic or silicon alternatives 613. For applications requiring enhanced heat dissipation, several strategies are employed:

• Incorporation of high-thermal-conductivity glass compositions (e.g., aluminum nitride-doped glasses with κ up to 3.5 W/(m·K)) 13
• Integration of embedded thermal vias or heat spreaders within the glass core 9
• Use of metal-clad glass laminates with copper or aluminum sheets bonded to core surfaces (achieving effective κ of 50–200 W/(m·K) in the through-thickness direction) 13

Glass transition temperature (Tg): Unlike organic substrates that exhibit distinct Tg transitions (typically 170–180°C for FR-4), glass cores maintain dimensional stability and mechanical properties across the entire operating temperature range of electronic assemblies 614. This eliminates concerns about CTE discontinuities and warpage associated with Tg transitions in organic materials.

Mechanical Properties And Reliability

Glass core substrate sheets must balance the inherent brittleness of glass with the mechanical demands of IC packaging:

Flexural strength: Laminated glass core structures achieve flexural strength of 150–250 MPa through engineered residual stress profiles 61416. By selecting glass compositions with differential CTE—core glass with higher CTE than skin layers—compressive stress of 1,000–3,000 psi (6.9–20.7 MPa) is induced in the surface layers during cooling from the bonding temperature 614. This compressive stress must overcome tensile stress before crack initiation, significantly enhancing impact resistance.

The core layer experiences residual tensile stress, typically maintained below 4,000 psi (27.6 MPa) to permit scribing and singulation without spontaneous fracture 614. Interlayers between core and skin can be engineered to further optimize the stress distribution, reducing core tensile stress while maintaining surface compression 616.

Warpage control: Glass cores exhibit superior flatness compared to organic substrates, with as-fabricated warpage typically <50 μm over 300 mm × 300 mm panels 12. This flatness is maintained through processing and assembly due to the high elastic modulus of glass (60–90 GPa) and absence of moisture-induced dimensional changes 6. In contrast, organic substrates commonly exhibit warpage of 200–500 μm due to CTE mismatch between copper and resin, moisture absorption, and residual stress from lamination 3.

Crack mitigation strategies: Several design and process innovations address glass brittleness 5717:

• Laser-induced nanoporosity gradients at via walls and substrate edges, which deflect crack propagation and increase fracture toughness 5
• Controlled phosphorus content (≤5 mass%) in nickel plating layers to minimize internal stress and prevent plating-induced cracking 7
• Incorporation of polymer or metal inserts in high-stress regions (e.g., around LGA notches) to provide localized compliance and arrest crack propagation 12
• Optimized singulation processes using laser scribing followed by controlled mechanical breaking, with laser-treated separation zones exhibiting higher nanoporosity to guide fracture paths 5

Applications Of Glass Core Substrate Sheets In Advanced Electronics

High-Performance Computing And Data Center Applications

Glass core substrate sheets have gained significant traction in high-performance computing (HPC) and artificial intelligence (AI) accelerator packages, where signal integrity, power delivery, and thermal management are paramount 123. These applications demand:

Ultra-high interconnect density: Modern HPC processors and AI accelerators require thousands of I/O connections with pitch as fine as 40–80 μm 15. Glass core substrates enable this density through:

• Fine-pitch TGVs (50–100 μm diameter, 100–150 μm pitch) providing vertical connectivity 12
• Redistribution layers with 2/2 μm line/space capability, supporting >10,000 connections/cm² 3
• Low Dk enabling tighter trace spacing without excessive crosstalk 5

High-speed signal transmission: For data rates exceeding 56 Gbps (PAM4) and extending to 112 Gbps and beyond, glass substrates provide measurable advantages 25:

• Insertion loss reduction of 20–30% compared to organic substrates at 28 GHz (56 Gbps NRZ Nyquist frequency) 1
• Improved eye diagram opening and reduced bit error rates, enabling longer electrical reach and reducing reliance on power-hungry retimers 5
• Stable impedance and minimal skew across wide temperature ranges, simplifying signal integrity validation 2

Power delivery network (PDN) optimization: The low Dk of glass reduces parasitic capacitance in power planes, while the ability to incorporate embedded capacitors or integrate thin-film capacitors directly on the glass surface enables low-inductance PDN designs with target impedance <0.5 mΩ at frequencies up to 1 GHz 13.

Case Study: Multi-Die HPC Package With Glass Core Substrate — High-Performance Computing: A leading semiconductor manufacturer developed a 2.5D package integrating four compute dies and eight HBM (High Bandwidth Memory) stacks on a glass core substrate 13. The substrate featured:

• 300 mm × 300 mm glass core with 100 μ