Redistribution Layer Glass Core Substrate: Advanced Architectures And Manufacturing Strategies For High-Density Semiconductor Packaging

Structural Design And Core Layer Engineering Of Redistribution Layer Glass Core Substrate

The fundamental architecture of redistribution layer glass core substrate comprises a glass core layer with precisely engineered through-glass vias (TGVs), bonded to one or more redistribution layers that provide fine-pitch routing and chip-to-package interconnection 2,17. The glass substrate typically exhibits a first surface and a second surface with core vias penetrating in the thickness direction, where the core via geometry critically influences electrical performance and mechanical reliability 2. Recent implementations demonstrate core via designs with a first surface opening diameter of 30–80 μm, a second surface opening diameter of 25–70 μm, and a minimum inner diameter positioned between openings to optimize via filling and minimize parasitic capacitance 2.

Key structural parameters include:

• Glass thickness: 50–300 μm for standard applications, with ultra-thin variants at 30–50 μm for mobile and wearable devices 1,16
• TGV diameter: 20–100 μm with aspect ratios (depth/diameter) ranging from 3:1 to 10:1, filled via electroplating or conductive paste to achieve vertical conductivity <10 mΩ per via 2,17
• Core distribution layer composition: Electrically conductive layers (typically Cu with 2–18 μm thickness) patterned on glass surfaces, comprising first surface core patterns, second surface core patterns, and core via patterns that maintain an average distance ≤1 μm between the conductive layer and the TGV inner wall to ensure reliable electrical contact 2
• Redistribution layer stack: Multiple sublayers (typically 2–8 layers) of conductive traces (5–50 μm line/space) formed in organic dielectric materials (polyimide, benzocyclobutene, or polybenzoxazole) with dielectric constants of 2.8–3.5 and breakdown voltages >100 V/μm 7,10

The integration of glass cores with RDLs enables disaggregated architectures where distinct blocks of redistribution layers are formed on a single glass substrate, each optimized for specific functional domains (e.g., high-speed digital, analog/RF, power delivery) 7. This approach allows first blocks and second blocks of RDLs to be fabricated with different trace widths—for instance, first routing layers with 50 μm traces for power distribution and second routing layers with 2–5 μm traces for fine-pitch chip interconnection—thereby optimizing cost and performance trade-offs 5,7.

Advanced designs incorporate multi-layer glass laminates to enhance mechanical strength and thermal performance 11,16. A representative structure includes a first glass layer, a second glass layer, and a third glass layer bonded via first and second bonding layers (typically 5–20 μm thick adhesive or glass frit), with conductive connectors passing through all layers to provide vertical conductive paths 11. This laminated approach increases the effective substrate thickness to 200–500 μm while maintaining low CTE and enabling embedded passive components or microfluidic channels for thermal management 10,11.

Material Selection And Thermal-Mechanical Properties For Glass Core Substrates

Material selection for redistribution layer glass core substrate is governed by stringent requirements for CTE matching, dielectric performance, and mechanical robustness 6,12. The glass core must exhibit a CTE closely matched to silicon (2.6 ppm/°C) and common die attach materials to minimize thermomechanical stress during thermal cycling (typically -40°C to 125°C for automotive, -55°C to 150°C for aerospace) 1,13.

Glass Core Material Specifications

Preferred glass compositions include:

• Borosilicate glass: CTE 3.3–5.0 ppm/°C, Young's modulus 63–70 GPa, dielectric constant (εr) 4.6–5.2 at 1 MHz, suitable for cost-sensitive applications with moderate thermal cycling 12,13
• Aluminosilicate glass: CTE 7.5–9.0 ppm/°C, Young's modulus 70–85 GPa, εr 5.8–6.5, offering higher strength (flexural strength 150–200 MPa) for applications requiring enhanced impact resistance 12,13
• Fused silica: CTE 0.5–0.8 ppm/°C, Young's modulus 73 GPa, εr 3.8, tan δ <0.0001 at 10 GHz, ideal for ultra-low-loss RF and high-frequency digital applications but at higher cost 10

The glass laminate substrate architecture employs a transparent glass core bounded by transparent glass skin layers, where the CTE of the core exceeds that of the skin layers (e.g., core CTE 9 ppm/°C, skin CTE 3.3 ppm/°C) to induce residual compressive stress (50–150 MPa) in the skin layers and residual tensile stress (20–60 MPa) in the core 12,13. This stress engineering enhances impact resistance and static load strength by factors of 2–4× compared to monolithic glass, while maintaining scribing and separation capability by controlling core tensile stress below 80 MPa 12,13. Optional interlayers (10–50 μm thick, CTE 5–7 ppm/°C) between core and skin further reduce core tensile stress to <40 MPa, enabling thinner substrates without compromising mechanical integrity 13.

Conductor And Dielectric Layer Materials

The core distribution layer employs a first nickel plating layer (0.5–2 μm thick) with phosphorus content ≤5 mass% to minimize cracking susceptibility, followed by a first copper plating layer (2–18 μm thick) for low-resistance routing 6. Electroless nickel plating with controlled phosphorus content (2–5 mass%) provides superior adhesion to glass (peel strength >0.8 N/mm) and reduces internal stress compared to high-phosphorus (>8 mass%) deposits, thereby preventing delamination during thermal excursions 6. Electrolytic copper plating achieves sheet resistance <0.5 mΩ/sq at 10 μm thickness, with grain sizes of 0.5–2 μm for optimal electromigration resistance 6.

Redistribution layer dielectrics include:

• Polyimide: εr 3.2–3.5, tan δ 0.002–0.008 at 10 GHz, glass transition temperature (Tg) 350–400°C, moisture absorption <1.5%, suitable for high-temperature processing and reliability 7,15
• Benzocyclobutene (BCB): εr 2.65, tan δ 0.0008 at 10 GHz, Tg 350°C, excellent planarization and low-k performance for RF applications 10
• Polybenzoxazole (PBO): εr 2.8, tan δ 0.003 at 10 GHz, Tg >400°C, superior chemical resistance and dimensional stability for advanced nodes 15

Organic dielectric layers are typically 5–20 μm thick per sublayer, with total RDL stack thickness of 30–150 μm depending on the number of routing layers 7,10.

Manufacturing Processes And Yield Optimization For Glass Core Substrates With Redistribution Layers

Manufacturing redistribution layer glass core substrate involves sequential processes of glass preparation, TGV formation, metallization, RDL fabrication, and lamination, each requiring precise control to achieve target yields >95% for high-volume production 2,6,15,17.

Through-Glass Via Formation And Metallization

TGV fabrication employs laser drilling (CO₂, picosecond, or femtosecond lasers) or mechanical drilling to create via holes with diameters of 20–100 μm and depths of 50–300 μm 2,11,16. Laser drilling parameters include:

• CO₂ laser: Wavelength 10.6 μm, pulse duration 10–100 μs, energy 0.5–2 J/pulse, suitable for borosilicate glass with drilling rates of 50–200 μm/s and taper angles of 5–15° 11
• Picosecond laser: Wavelength 355–1064 nm, pulse duration 10–50 ps, energy 10–100 μJ/pulse, enabling near-vertical sidewalls (taper <3°) and reduced heat-affected zones (<5 μm) for high-aspect-ratio vias 16

Post-drilling, via sidewalls undergo surface treatment (wet etching in HF/HNO₃ or plasma cleaning) to remove debris and enhance wettability, followed by seed layer deposition via sputtering (Ti/Cu 50/200 nm) or electroless plating (Ni/Cu 0.5/1 μm) 2,6,17. Electrolytic copper plating fills the vias at current densities of 1–5 A/dm² with plating times of 30–120 minutes, achieving void-free filling and via resistance <10 mΩ 2,17. The core via pattern maintains an average distance ≤1 μm between the plated copper and the via inner wall, ensuring low contact resistance and high reliability under thermal cycling (ΔR/R₀ <5% after 1000 cycles -40°C to 125°C) 2.

Redistribution Layer Fabrication And Patterning

RDL fabrication on glass cores follows a build-up process:

1. Dielectric layer deposition: Spin-coating or lamination of polyimide or BCB precursors at 10–20 μm thickness, followed by soft bake (80–120°C, 5–10 min), exposure (UV 200–400 mJ/cm² for photosensitive types), development, and hard cure (300–400°C, 1–2 hours in N₂) 7,15
2. Via opening formation: Laser ablation (CO₂ or UV) or reactive ion etching (RIE) to create microvias (10–50 μm diameter) connecting RDL layers, with via depth tolerance ±2 μm 15
3. Seed layer deposition: Sputtering Ti/Cu (50/200 nm) or electroless Cu (0.5 μm) to provide a conductive base for electroplating 6,15
4. Photoresist patterning: Spin-coating dry film or liquid photoresist (5–20 μm thick), exposure (150–300 mJ/cm²), and development to define trace patterns with 2–50 μm line/space 7,15
5. Electrolytic copper plating: Plating at 1–3 A/dm² to deposit 5–18 μm Cu traces, followed by photoresist stripping and seed layer etching 6,15
6. Antioxidant layer formation: Electroless plating of Ni/Au (3–5 μm Ni, 0.05–0.2 μm Au) on exposed Cu pads to prevent oxidation and ensure bondability 15

Multiple RDL sublayers (2–8 layers) are sequentially built up, with each cycle adding 15–30 μm to the total stack thickness 7,10. Advanced processes incorporate semi-additive patterning (SAP) to achieve sub-5 μm line/space, using thin seed layers (50–100 nm Cu) and selective electroplating to minimize etching undercut 15.

Lamination And Bonding Techniques

Glass core substrates are laminated with sub-circuit boards or additional glass layers to form multi-layer structures 11,15,16. The lamination process involves:

• Pre-lamination preparation: Sub-circuit boards (e.g., prepreg with glass fiber reinforcement) in B-stage state (partially cured) are aligned with the glass core and RDL using optical alignment marks (±5 μm accuracy) 15
• Hot pressing: Lamination at 180–220°C, 20–40 bar pressure, for 60–120 minutes in vacuum (<10 mbar) to transform the sub-circuit board from B-stage to C-stage (fully cured) and achieve bond line thickness of 10–30 μm 15
• Conductive through-hole formation: Laser drilling through the sub-circuit board to create through-holes (50–200 μm diameter), followed by filling with conductive metal adhesive (Ag-filled epoxy with resistivity <10⁻⁴ Ω·cm) to establish vertical interconnection without electroplating 15

For glass-to-glass bonding, bonding layers (5–20 μm thick) of glass frit, adhesive, or anodic bonding are employed 11,16. Glass frit bonding at 400–600°C provides hermetic seals and CTE-matched interfaces, while adhesive bonding (epoxy or polyimide) at 150–250°C offers lower thermal budgets suitable for pre-fabricated RDLs 11,16.

Yield Enhancement And Defect Mitigation

Critical yield detractors include:

• TGV voiding: Mitigated by optimizing plating current profiles (pulse plating at 1–5 A/dm² with 10–50 ms on-time, 5–20 ms off-time) and via aspect ratio control (<8:1) 2,17
• Glass cracking: Reduced by controlling nickel plating phosphorus content (≤5 mass%), minimizing residual tensile stress in the core (<60 MPa), and employing arc-profile or stepped scribed surfaces to distribute stress 1,6,12
• RDL delamination: Prevented by ensuring dielectric adhesion >0.8 N/mm via surface plasma treatment (O₂ or Ar, 100–300 W, 30–60 s) and controlling moisture absorption (<1.5%) through bake-out (120°C, 4–8 hours) prior to lamination 15
• Warpage: Managed by symmetric RDL stack design (balanced metal density on both sides of the glass core) and stress-relief grooves (50–200 μm wide, 10–50 μm deep) formed around the periphery of the redistribution structure to accommodate CTE mismatch 1,14

Inline metrology (automated optical inspection, X-ray inspection, electrical continuity testing) at each process step enables real-time feedback and defect classification, achieving defect densities <10 defects/m² for production-worthy substrates 2,17.

Thermal Management And Microfluidic Integration In Glass Core Substrates

Advanced redistribution layer glass core substrates incorporate in-situ microfluidic channels within the glass core to enhance thermal dissipation for high-power applications (e.g., AI accelerators with power densities >100 W/cm²) 10. The microfluidic channels (50–500 μm width, 50–300 μm depth) are formed via laser ablation or wet etching prior to RDL