Silicon Device High Voltage Material: Advanced Substrates And Architectures For Power Electronics

Fundamental Material Properties And Voltage Blocking Mechanisms Of Silicon Device High Voltage Material

High voltage silicon devices rely on carefully engineered material properties to achieve breakdown voltages far exceeding those of conventional silicon transistors. The voltage blocking substrate is central to this capability: it must exhibit high purity, controlled carrier concentration, and sufficient thickness to support the electric field distribution under reverse bias 1,6,7. For silicon carbide (SiC) implementations, a 4H-SiC polytype substrate with carrier concentration ≤10×10¹⁵ cm⁻³ and thickness >100 μm is typical 1,6,7,12. This combination yields a critical electric field strength of approximately 2–3 MV/cm, roughly an order of magnitude higher than silicon's ~0.3 MV/cm, enabling thinner drift regions and lower specific on-resistance for a given blocking voltage 1,6.

Silicon-on-insulator (SOI) architectures achieve high voltage capability through dielectric isolation: a buried oxide (BOX) layer separates active device regions from the handle wafer, preventing vertical leakage paths and enabling multiple high-voltage circuits in close proximity without inter-circuit breakdown 2,3,4,5. Devices fabricated on bonded and vertically trenched SOI substrates demonstrate breakdown voltages ≥100 V, with optimized designs reaching ≥350 V 2,3,4,5. The trench width and BOX thickness must be dimensioned to withstand the maximum operating voltage; for example, a 1-μm BOX supports ~30 V/μm, requiring ~12 μm for 350 V operation 2.

Key material parameters include:

• Carrier concentration: SiC substrates: ≤10×10¹⁵ cm⁻³ 1,6,7; SOI active layers: tailored via epitaxy or ion implantation to 10¹⁶–10²¹ cm⁻³ depending on device type 12.
• Substrate thickness: SiC: >100 μm 1,6,7; SOI handle wafer: 300–725 μm (standard); active silicon layer: 0.5–20 μm 2,12.
• Dielectric strength: SiC BOX equivalent: >5 MV/cm; thermal SiO₂: ~10 MV/cm 2,12.
• Thermal conductivity: 4H-SiC: ~3.7 W/cm·K vs. Si: ~1.5 W/cm·K, critical for power dissipation 1,6.

The bi-directional blocking capability in SiC thyristors and diodes arises from symmetric pnpn or pn junction stacks on both substrate faces, each engineered to support half the total blocking voltage 1,6,7,14. This symmetry is achieved by epitaxial growth of doped SiC layers (e.g., p-type on n-type substrate, then n⁺ contact layers) on both surfaces, with carrier concentrations and thicknesses optimized via TCAD simulation to balance forward and reverse breakdown 1,6,14.

Silicon Carbide Substrates For High Voltage Silicon Device Applications

Silicon carbide substrates represent the premier material platform for silicon device high voltage applications due to their superior physical and electronic properties. Boule-grown 4H-SiC substrates are the industry standard, offering high crystalline quality and scalable wafer diameters (currently 150–200 mm, with 200 mm in volume production) 1,6,7. The growth process—typically physical vapor transport (PVT) at ~2300°C—yields substrates with minority carrier lifetimes >1 μs when optimized, a critical parameter for bipolar devices such as thyristors and IGBTs 1,6.

Substrate Specifications And Performance Metrics

• Polytype: 4H-SiC preferred for power devices due to higher electron mobility (~1000 cm²/V·s) and lower anisotropy than 6H-SiC 1,6,7.
• Doping: n-type (nitrogen) or p-type (aluminum) with net carrier concentration 10¹⁴–10¹⁶ cm⁻³; ultra-high-purity grades (<5×10¹⁴ cm⁻³) enable >10 kV blocking 1,6,7.
• Micropipe density: <0.1 cm⁻² for device-grade wafers; modern substrates approach zero micropipes via optimized seeding 1.
• Surface roughness: <0.5 nm RMS after chemical-mechanical polishing (CMP), essential for high-quality epitaxy 1,6.

Epitaxial Layer Engineering

High voltage SiC devices require one or more epitaxial layers atop the substrate to form drift regions, channel layers, and contact regions. For a 1200 V-class device, a lightly doped n-type drift layer (Nᴅ ~10¹⁵–10¹⁶ cm⁻³, thickness 10–15 μm) is grown via chemical vapor deposition (CVD) at 1500–1600°C using silane (SiH₄) and propane (C₃H₈) precursors 1,6,12. Doping is controlled in situ by adding nitrogen (for n-type) or trimethylaluminum (for p-type) 1,6. The first SiC layer on the substrate typically has thickness 0.1–20 μm and carrier concentration 10¹⁶–10²¹ cm⁻³, tailored to the device architecture (e.g., p⁺ anode layer for thyristors, p-base for IGBTs) 12.

Advantages Over Silicon

• 10× higher breakdown field: Enables 10× thinner drift regions for equivalent blocking voltage, reducing on-resistance by ~100× 1,6.
• 3× higher thermal conductivity: Facilitates higher current density and smaller die size 1,6.
• Wide bandgap (3.26 eV): Supports operation at junction temperatures >200°C without intrinsic carrier effects 1,6.

Silicon-On-Insulator (SOI) Architectures For High Voltage Integration

SOI technology provides a pathway to integrate high voltage switching circuits (≥100 V) with low- and intermediate-voltage CMOS and bipolar circuits on a single substrate, a capability unattainable with bulk silicon due to latch-up and substrate coupling 2,3,4,5. The core innovation is dielectric isolation via buried oxide (BOX) and vertical trench isolation, which partition the active silicon layer into electrically independent tubs 2,3,4,5.

Substrate Fabrication And Trench Isolation

A bonded SOI wafer is formed by thermally oxidizing a silicon wafer (forming ~1–2 μm SiO₂), bonding it to a handle wafer, and thinning the top wafer to the desired active layer thickness (0.5–10 μm for high voltage devices) 2,3,4,5. Vertical trenches are then etched anisotropically (e.g., reactive ion etching with SF₆/O₂ plasma) through the active layer to the BOX, defining isolated silicon islands 2,3,4,5. Trench width must accommodate the lateral depletion width at maximum voltage; for 350 V DMOS, a 5–10 μm trench filled with TEOS oxide is typical 2,4.

High Voltage DMOS On SOI

Double-diffused MOS (DMOS) transistors on SOI achieve breakdown voltages ≥350 V by employing a lightly doped drift region between the channel and drain, which supports the off-state electric field 2,3,4,5. Key fabrication steps include:

1. N-well formation: Phosphorus implant (dose ~10¹³ cm⁻², energy 100–200 keV) and drive-in diffusion at 1100°C for 4–6 hours, creating an n-type tub with surface concentration ~10¹⁶ cm⁻³ and depth 3–5 μm 2,3.
2. P-body implant: Boron implant (dose ~10¹³ cm⁻², energy 50–80 keV) within the n-well, forming the channel region 2,3.
3. Gate stack: Thermal oxidation (50–100 nm SiO₂) followed by LPCVD polysilicon (300–500 nm) deposition and patterning 2,3,4.
4. Source/drain formation: Arsenic or phosphorus implant (dose ~10¹⁵ cm⁻², energy 40–60 keV) for n⁺ source/drain, with the drain extending to the n⁺ wraparound layer at the trench sidewall to minimize resistance 2,3,4.
5. Edge oxidation: Controlled re-oxidation of the polysilicon gate edges forms 100–200 nm thick oxide "bird's beaks," increasing the gate-to-drain breakdown voltage by reducing the peak electric field at the gate corner 2,3,4.

Measured performance: breakdown voltage 350–600 V, specific on-resistance 10–50 mΩ·cm², gate threshold voltage 2–4 V 2,3,4,5.

Co-Integration With Low Voltage CMOS And Bipolar Circuits

The same SOI substrate can host:

• CMOS logic (5–20 V): Standard twin-well process in adjacent tubs, with gate oxide 5–10 nm and channel lengths 0.18–1 μm 2,3,4,5.
• Bipolar transistors (≤100 V): NPN or PNP structures formed by selective implants (e.g., p-base, n⁺ emitter, n⁺ collector) in isolated tubs, with breakdown voltage set by collector doping and width 2,3,4,5.
• High voltage DMOS (≥350 V): As described above, in wider tubs with thicker BOX and trench spacing 2,3,4,5.

This BCDMOS (Bipolar-CMOS-DMOS) integration enables system-on-chip solutions for applications such as line card access switches (telecom), motor drivers (automotive), and power management ICs, reducing component count and board area by 50–70% compared to discrete implementations 2,3,4,5.

Device Architectures And Design Considerations For Silicon Device High Voltage Material

SiC Thyristors And Bidirectional Switches

SiC thyristors are four-layer pnpn structures capable of blocking high voltages in both forward and reverse directions, making them ideal for AC switching and solid-state circuit breakers 1,6,7,14. A typical symmetric thyristor comprises:

• Substrate: p-type 4H-SiC, 100–300 μm thick, Nᴀ ~10¹⁵ cm⁻³ 1,6,7,14.
• First n-layer: Epitaxial n-type SiC on substrate top surface, 0.5–2 μm thick, Nᴅ ~10¹⁷ cm⁻³ 1,6,14.
• P⁺ anode region: Ion implantation (Al, dose ~10¹⁴ cm⁻², 100 keV) and activation anneal (1600°C, 30 min in Ar), forming p⁺ contact with concentration ~10¹⁹ cm⁻³ 1,6,14.
• N⁺ cathode region: Implanted into the first n-layer adjacent to the p⁺ anode, Nᴅ ~10²⁰ cm⁻³ 1,6,14.
• Second n-layer: Epitaxial n-type SiC on substrate bottom surface, symmetric to the first n-layer 1,6,7,14.
• P⁺ and n⁺ regions on bottom: Mirror the top structure for bidirectional blocking 1,6,7,14.

Forward blocking voltage is determined by the p-substrate thickness and doping; for a 100 μm, 10¹⁵ cm⁻³ substrate, Vʙʀ ~3–5 kV 1,6,7. Reverse blocking is symmetric. On-state voltage drop is 3–4 V at 100 A/cm² due to the pnpn junction drops 1,6,14.

SiC IGBTs With Planar And Beveled Edge Termination

Insulated gate bipolar transistors (IGBTs) combine the high input impedance of MOSFETs with the low on-state drop of bipolar transistors, suitable for >1200 V applications 12. A SiC IGBT structure includes:

• Voltage blocking substrate: n-type 4H-SiC, 100–150 μm, Nᴅ ~5×10¹⁵ cm⁻³ 12.
• P-base layer: Epitaxial p-type SiC, 0.5–1 μm, Nᴀ ~10¹⁷ cm⁻³, on substrate top 12.
• N⁺ source and p⁺ contact regions: Implanted in p-base, with n⁺ source adjacent to the gate-controlled channel 12.
• Gate stack: 50 nm thermal SiO₂ + 400 nm polysilicon, patterned to control the channel between source and drift region 12.
• P⁺ collector layer: Epitaxial p-type SiC on substrate bottom, Nᴀ ~10¹⁸ cm⁻³, forming the collector contact 12.

Edge termination is critical to approach the theoretical breakdown voltage. Two techniques are combined 12:

1. Planar termination (top surface): Junction termination extension (JTE) via shallow p-type implant (dose 10¹²–10¹³ cm⁻², energy 30–50 keV) extending 20–50 μm beyond the active area, grading the electric field and increasing breakdown voltage by 20–30% 12.
2. Beveled termination (bottom surface): Mechanical or plasma etching creates a 5–15° bevel angle over 50–100 μm, reducing the surface electric field at the collector junction edge and preventing premature breakdown 12.

With dual termination, 1200 V-class SiC IGBTs achieve breakdown voltage >1500 V, on-state voltage drop ~2.5 V at 100 A/cm², and switching times <100 ns 12.

High Voltage Semiconductor Devices On SOI With Field Plate Structures

Advanced SOI high voltage devices incorporate field plate electrodes to redistribute the electric field and increase breakdown voltage without enlarging the drift region 9. The field plate is a conductive layer (typically polysilicon or metal) positioned over the drift region between the gate and drain, separated by a thick dielectric (e.g., 500 nm TEOS oxide) 9. By biasing the field plate (often connected to the source or gate), the lateral electric field is spread more uniformly, reducing the peak field at the gate edge by 30–40% and increasing Vʙʀ by 20–50 V for a given drift length 9.

A representative structure includes 9:

• First semiconductor layer: Buried p-type polysilicon between two oxide layers (BOX below, isolation oxide above), acting as a field-shaping electrode 9.
• **Second and third semiconductor layers