Silicon Device Contact Material: Advanced Metallization Systems And Fabrication Strategies For High-Performance Semiconductor Applications

Fundamental Contact Material Systems For Silicon And Silicon Carbide Devices

Electrical contacts in silicon device architectures serve as the critical interface between semiconductor active regions and external circuitry, with material selection governing contact resistance, thermal budget compatibility, and mechanical robustness 1. For conventional silicon devices, early approaches employed gold-cobalt bilayers deposited on silicon substrates, where gold (Au) was first deposited followed by cobalt (Co), and the structure was annealed at 300–370°C in a reducing atmosphere to form a stable, low-resistance contact 1. This method leveraged cobalt's superior barrier properties compared to gold alone, reducing porosity and preventing oxidation of underlying layers while maintaining acceptable contact resistance in the range of several tens of ohms 1.

In silicon carbide (SiC) devices—critical for high-temperature and high-power applications—contact material requirements are more stringent due to SiC's wide bandgap and chemical inertness 2. Titanium silicon carbide (Ti₃SiC₂) has emerged as a thermodynamically stable contact material for SiC components, exhibiting no reaction with SiC substrates up to 1200°C 2. This ternary compound is typically deposited via pulsed laser deposition, sputtering, or chemical vapor deposition, ensuring single-phase stoichiometry and microstructural control 2. The absence of interfacial reactions across the Ti₃SiC₂/SiC junction preserves consistent electrical resistance over prolonged high-temperature operation, a critical advantage for sensors and actuators in corrosive or extreme thermal environments 2.

For both n-type and p-type SiC, nickel-aluminum (Ni-Al) contact systems provide dual functionality: forming Schottky contacts on n-SiC and ohmic p-contacts on p-SiC after a single annealing step at approximately 1000°C 6. This co-annealability simplifies fabrication of complex devices such as pinch diodes, where alternating n- and p-regions require simultaneous contact formation without degrading Schottky barrier characteristics 6. The Ni-Al metallization, typically 200 nm thick, is often reinforced with an aluminum capping layer and a nickel or nickel-iron back-surface contact, all annealed together to achieve low specific contact resistivity (ρ_c) and robust adhesion 6.

Nickel Silicide Ohmic Contacts In Silicon Carbide Power Devices

Nickel silicide (NiSi_x) layers have become the industry standard for forming low-resistance ohmic contacts in silicon carbide field-effect transistors (FETs) and diodes, particularly in self-aligned fabrication processes 3,4,11,13. The formation mechanism involves depositing a blanket nickel layer over both the dielectric-covered gate electrode and exposed contact regions (source, drain), followed by rapid thermal annealing (RTA) at temperatures typically between 950°C and 1050°C 3,11. During annealing, nickel reacts with silicon from the SiC substrate in contact regions to form nickel silicide species (Ni₂Si, NiSi), while nickel over the dielectric remains unreacted and is subsequently etched away selectively 3,4.

Key advantages of this approach include:

• Self-alignment: The silicide forms only where nickel contacts SiC, eliminating the need for lift-off techniques that can cause rough edges, stringers, torn contacts, and poor adhesion 3,4.
• Low specific contact resistance: Optimized NiSi contacts achieve ρ_c values in the range of 10⁻⁵ to 10⁻⁶ Ω·cm² on heavily doped n⁺ SiC (doping >10¹⁹ cm⁻³), suitable for minimizing on-resistance (R_on) in power MOSFETs 11,13.
• Thermal stability: Nickel silicide phases remain stable during subsequent high-temperature processing steps (e.g., interlayer dielectric deposition, metallization annealing), preserving contact integrity 3,11.
• Compatibility with standard CMOS toolsets: Nickel deposition and RTA are mature unit processes, facilitating technology transfer from silicon to SiC platforms 4,13.

Experimental data from General Electric's SiC MOSFET development indicate that a 100 nm nickel layer annealed at 1000°C for 60 seconds in nitrogen ambient yields a nickel silicide contact with sheet resistance <50 Ω/sq and contact resistance <1×10⁻⁵ Ω·cm² on n⁺ SiC epilayers doped at 5×10¹⁹ cm⁻³ 3,11. The annealing atmosphere (N₂, Ar, or forming gas) and ramp rate critically influence silicide phase composition and interface abruptness; forming gas (5% H₂ in N₂) is often preferred to minimize oxidation and carbon accumulation at the NiSi/SiC interface 13.

Polysilicon Interlayer Contacts For Enhanced Adhesion And Reduced Thermal Budget

An alternative contact architecture employs a polysilicon (poly-Si) interlayer between the SiC substrate and metal contact, addressing adhesion challenges and enabling lower-temperature processing 7. In this scheme, a thin poly-Si layer (typically 50–200 nm) is deposited on the SiC surface via low-pressure chemical vapor deposition (LPCVD) at 600–650°C, followed by metal deposition (e.g., nickel, titanium, or aluminum) on the poly-Si 7. The poly-Si can be undoped, n-type, or p-type doped to match the underlying SiC region, and may be patterned or left continuous depending on device geometry 7.

Benefits of the poly-Si interlayer approach include:

• Elimination of high-temperature annealing: Ohmic contact formation occurs at the poly-Si/metal interface rather than the SiC/metal interface, reducing the required annealing temperature from >1050°C to <900°C and avoiding carbon-rich interfacial layers that degrade adhesion 7.
• Improved mechanical robustness: Poly-Si provides a compliant buffer layer that accommodates thermal expansion mismatch between SiC (α ≈ 4.5×10⁻⁶ K⁻¹) and metals (α ≈ 10–20×10⁻⁶ K⁻¹), reducing stress-induced delamination 7.
• Versatility: Both Schottky and ohmic contacts can be realized by tuning poly-Si doping and metal work function, enabling monolithic integration of diodes, transistors, and passive components on a single SiC chip 7.

Experimental results from Rockwell Scientific demonstrate that a 100 nm n⁺ poly-Si layer (phosphorus-doped, 10²⁰ cm⁻³) capped with 200 nm nickel and annealed at 850°C for 30 minutes yields specific contact resistance ρ_c ≈ 5×10⁻⁵ Ω·cm² on n-SiC, with no measurable degradation after 1000 hours at 300°C 7. Adhesion testing (tape test, die shear) showed no delamination, contrasting with direct Ni/SiC contacts annealed at 1050°C, which exhibited partial lift-off due to nickel silicide stress 7.

Multilayer Metal Stacks For Silicon Devices: Nickel-Gold-Cobalt Systems

For conventional silicon power devices and discrete components, multilayer metal stacks provide optimized combinations of low contact resistance, oxidation resistance, and solderability 5. A representative structure comprises a sintered nickel base layer on silicon, an intermediate gold layer, and a cobalt capping layer 5. The fabrication sequence involves:

1. Nickel plating and sintering: Electroless or electroplated nickel (2–5 μm) is deposited on silicon and sintered at 575–625°C for 10–30 minutes in 10% H₂/90% N₂ atmosphere, forming nickel silicide (Ni₂Si) at the interface and establishing an ohmic contact with sheet resistance ~10 Ω/sq 5.
2. Gold deposition: A 0.5–2 μm gold layer is plated over the sintered nickel. Gold alloys with nickel at temperatures >300°C (achievable during subsequent soldering operations), strengthening the Ni-Au bond and providing a noble-metal surface for wire bonding or soldering 5.
3. Cobalt capping: A 0.2–1 μm cobalt layer is deposited on gold. Cobalt is less porous than gold at comparable thickness, offering superior protection against oxidation of the underlying nickel silicide, and forms a strong bond with gold without additional processing 5.

This Ni-Au-Co stack achieves contact resistance <10⁻⁴ Ω·cm², withstands soldering temperatures up to 350°C, and exhibits <5% resistance increase after 2000 hours at 150°C in air 5. The cobalt layer's low porosity (measured via electrochemical impedance spectroscopy at <0.1% pinhole density for 0.5 μm thickness) ensures long-term reliability in humid or corrosive environments 5. Compared to Ni-Au contacts without cobalt, the Ni-Au-Co system reduces gold thickness requirements by ~50%, lowering material cost while maintaining equivalent oxidation resistance 5.

Heavily Doped Silicon Carbide Ohmic Contacts For High-Temperature And Radiation-Hard Applications

In specialized applications such as ultraviolet detectors and radiation-hard power rectifiers, ohmic contacts consisting entirely of heavily doped SiC (rather than metal) offer unique advantages 8. These contacts are fabricated by epitaxially growing or ion-implanting high-concentration dopant regions (n⁺ or p⁺, >10²⁰ cm⁻³) on the SiC device surface, creating a tunneling-dominated contact with negligible Schottky barrier 8. The SiC contact layer is then metallized with a refractory metal (e.g., tungsten, molybdenum) that forms a stable carbide interface 8.

Key performance characteristics include:

• Radiation tolerance: SiC-SiC homojunctions exhibit minimal degradation under neutron or gamma irradiation (fluence >10¹⁵ n/cm²), as displacement damage does not alter the contact's tunneling mechanism 8.
• High-temperature stability: Contacts remain ohmic up to 600°C, with contact resistance increasing <20% due to reduced carrier mobility rather than interfacial reactions 8.
• Simplified encapsulation: The absence of dissimilar metal-semiconductor interfaces eliminates galvanic corrosion concerns, allowing unencapsulated operation in harsh environments 8.

Experimental data from Westinghouse's SiC UV detector program show that n⁺ SiC contacts (nitrogen-doped, 2×10²⁰ cm⁻³) with tungsten metallization achieve ρ_c ≈ 10⁻⁴ Ω·cm² at 25°C and 5×10⁻⁴ Ω·cm² at 400°C, with junction depth optimized at 0.5 μm to balance contact resistance and optical absorption 8. Radiation testing (1 MeV neutron fluence 10¹⁶ n/cm²) resulted in <10% increase in contact resistance, compared to >200% increase for conventional Ni/SiC contacts under identical conditions 8.

Barrier Layer Structures And Copper Metallization In Advanced Silicon Carbide Devices

Modern SiC power modules increasingly adopt copper (Cu) metallization for top-level interconnects due to copper's lower resistivity (1.7 μΩ·cm vs. 2.7 μΩ·cm for aluminum) and superior electromigration resistance 12. However, copper diffuses rapidly into SiC and silicides at temperatures >400°C, necessitating robust diffusion barrier layers 12. A typical barrier stack comprises titanium (Ti) and tungsten (W) sublayers, with the contact sequence: SiC substrate → Ni-Si-Al contact layer → Ti adhesion layer (20–50 nm) → TiN or TiW barrier (50–100 nm) → W nucleation layer (50 nm) → Cu metallization (1–5 μm) 12.

The Ni-Si-Al contact layer (composition: Ni 70–80 at.%, Si 10–20 at.%, Al 5–15 at.%) is formed by co-sputtering or sequential deposition followed by RTA at 950–1000°C, yielding a homogeneous ternary phase with ρ_c < 10⁻⁵ Ω·cm² on both n⁺ and p⁺ SiC 12. Aluminum addition suppresses formation of high-resistivity Ni₃Si₂ and improves contact uniformity, as confirmed by transmission electron microscopy (TEM) showing a single-phase 50 nm interfacial layer with <5% composition variation 12.

The Ti/TiN/W barrier stack prevents copper diffusion up to 500°C for >10,000 hours, as verified by secondary ion mass spectrometry (SIMS) depth profiling showing copper concentration <10¹⁷ cm⁻³ at the barrier/contact interface after accelerated aging 12. Barrier integrity is critical for automotive and aerospace SiC modules, where junction temperatures routinely exceed 175°C and mission lifetimes demand >10⁵ hours mean time to failure (MTTF) 12.

Fabrication Process Optimization And Thermal Budget Management

Achieving low-resistance, reliable contacts in SiC devices requires careful optimization of deposition conditions, annealing profiles, and surface preparation 3,7,11. Key process parameters include:

• Surface cleaning: SiC surfaces must be free of native oxide (SiO₂) and organic contaminants prior to contact deposition. Standard cleaning sequences involve HF dip (5% HF, 60 s) to remove oxide, followed by piranha clean (H₂SO₄:H₂O₂ 3:1, 10 min at 120°C) and deionized water rinse 2,7. In situ plasma cleaning (Ar or H₂, 50 W, 2 min) immediately before metal deposition further reduces interfacial contamination 7.
• Annealing atmosphere and temperature: For nickel silicide formation, RTA in nitrogen or forming gas at 950–1050°C for 30–120 seconds is typical 3,11,13. Higher temperatures (>1050°C) promote formation of lower-resistivity NiSi phase but risk metal agglomeration and rough morphology; lower temperatures (<950°C) yield incomplete silicidation and higher ρ_c 13. Annealing in vacuum or inert gas minimizes oxidation, while forming gas reduces carbon accumulation at the silicide/SiC interface 13.
• Metal thickness and stoichiometry: For Ni-Si-Al contacts, the optimal nickel-to-aluminum atomic ratio is ~10:1 to 15:1, achieved by controlling sputter target composition or co-deposition rates 12. Excessive aluminum (>20 at.%) leads to formation of insulating Al₂O₃ at grain boundaries, increasing ρ_c; insufficient aluminum (<5 at.%) fails to suppress Ni₃Si₂ formation 12. Total contact layer thickness is typically 50–150 nm, balancing low resistance with minimal stress 12.
• Patterning and etching: Self-aligned silicide processes avoid lithographic misalignment but require selective wet etching of unreacted nickel (e.g., H₂SO₄:H₂O₂ 4:1 at 80°C, etch rate ~50 nm/min) without attacking the silicide or dielectric 3,4. Dry etching (Cl₂/