Through-Glass Via Copper Filled Substrate: Advanced Metallization Strategies And Hermetic Sealing Solutions For High-Density Interconnects

Fundamental Challenges In Through-Glass Via Copper Filled Substrate Fabrication

Through-glass via copper filled substrates face three interrelated technical barriers that distinguish them from conventional through-silicon via (TSV) processes. First, the absence of native oxide on glass surfaces prevents direct copper nucleation, necessitating intermediate adhesion promotion layers 2,8. Second, the large CTE mismatch induces circumferential and radial cracking during thermal cycling, particularly when cooling from electroplating temperatures (60–80°C) or subsequent reflow operations (>260°C) 7. Third, achieving void-free copper filling in vias with diameters <50 μm and aspect ratios >5 requires precise control of electrochemical deposition kinetics to avoid seam formation or incomplete bottom-fill 4,13.

The glass substrate itself introduces additional constraints: borosilicate and aluminosilicate compositions exhibit surface hydroxyl densities of 4–8 OH/nm², insufficient for robust metal adhesion without surface functionalization 6. Furthermore, glass substrates intended for RF applications demand low dielectric loss (tan δ <0.005 at 10 GHz), which restricts the choice of adhesion layer materials to those that do not introduce conductive pathways or increase parasitic capacitance 11. These requirements have driven the development of novel adhesion chemistries, hybrid plating sequences, and stress-relief architectures detailed in the following sections.

Adhesion Layer Engineering For Copper-Glass Interfaces In TGV Substrates

Manganese Oxide (MnOₓ) Adhesion Layers And Reduction Annealing Protocols

Manganese oxide adhesion layers deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD) have emerged as a leading solution for through-glass via copper filled substrates requiring hermetic sealing 2,8. The process sequence comprises: (i) deposition of 5–20 nm MnOₓ (x = 1.5–2.0) at 150–250°C, (ii) optional pre-annealing in oxidizing atmosphere (air, 300–400°C, 30–60 min) to densify the oxide network, (iii) catalyst activation with palladium colloids or electroless copper seed layer deposition, and (iv) post-plating reduction annealing in forming gas (5% H₂/N₂, 300–450°C, 1–2 h) to convert MnOₓ to metallic Mn or Mn-Cu intermetallic phases 2.

The reduction annealing step is critical: X-ray photoelectron spectroscopy (XPS) depth profiling reveals that annealing at 350°C for 90 min reduces Mn⁴⁺ and Mn³⁺ species to Mn²⁺ and Mn⁰, forming a graded interface with copper that exhibits peel strength >1.5 N/mm (90° peel test per IPC-TM-650) and helium leak rates <5×10⁻⁹ atm·cm³/s 8. The adhesion mechanism involves formation of Cu-Mn solid solution (up to 30 at% Mn solubility in copper at 400°C) and oxygen scavenging at the interface, which eliminates weak Cu-O-Si bonds 2. Comparative studies show that MnOₓ outperforms titanium adhesion layers (10–50 nm Ti by PVD) in both adhesion strength (1.5 vs. 0.8 N/mm) and hermeticity, while reducing total metallization thickness by 40–60 nm 8.

Silane-Based Self-Assembled Monolayers (SAMs) For Electroless Copper Nucleation

An alternative approach employs organosilane self-assembled monolayers (SAMs) to functionalize glass surfaces prior to electroless copper deposition 4,6,13. The process involves: (i) hydroxylation of glass surfaces by oxygen plasma (100 W, 30 s) or piranha solution (H₂SO₄:H₂O₂ = 3:1, 80°C, 10 min) to increase OH density to >6 OH/nm², (ii) immersion in 1–5 vol% aminopropyltriethoxysilane (APTES) or mercaptopropyltrimethoxysilane (MPTMS) in ethanol/water (95:5) at 60°C for 30–60 min, forming a 1.5–2.5 nm monolayer, and (iii) curing at 110°C for 15 min to complete siloxane condensation 6.

The terminal amine (-NH₂) or thiol (-SH) groups provide nucleation sites for palladium catalyst (PdCl₂ solution, 0.1–0.5 g/L Pd, pH 2–3, 5 min immersion) or directly reduce Cu²⁺ ions during electroless plating 4. Electroless copper baths formulated with CuSO₄ (8–12 g/L Cu²⁺), formaldehyde (2–4 mL/L as reducing agent), EDTA (20–30 g/L as complexing agent), and 2,2'-bipyridyl (5–10 mg/L as stabilizer) at pH 12.5–13.0 and 60–70°C deposit 0.5–1.5 μm seed layers at 1–3 μm/h with sheet resistance <50 mΩ/sq 13. This seed layer thickness is sufficient for subsequent electrolytic copper filling while maintaining total metallization thickness <15 μm, critical for high-frequency applications where skin depth at 10 GHz is ~2 μm 4.

Comparative Performance Of Adhesion Layer Systems

Quantitative adhesion testing (ASTM D3359 cross-hatch, 90° peel per IPC-TM-650 2.4.9, and die shear per JEDEC JESD22-B116) reveals distinct performance envelopes for different adhesion systems in through-glass via copper filled substrates:

• MnOₓ + reduction annealing: Peel strength 1.2–1.8 N/mm, die shear strength 45–65 MPa, helium leak rate <5×10⁻⁹ atm·cm³/s, thermal cycling reliability (−55 to 150°C, 1000 cycles per JEDEC JESD22-A104) with <5% resistance increase 2,8.
• Silane SAM + electroless Cu: Peel strength 0.8–1.2 N/mm, die shear strength 30–50 MPa, helium leak rate 1–5×10⁻⁸ atm·cm³/s, suitable for non-hermetic applications with cost advantage (no ALD/CVD equipment required) 4,6,13.
• Ti/TiN barrier + PVD Cu seed: Peel strength 0.6–1.0 N/mm, die shear strength 25–40 MPa, but total metallization thickness 80–150 nm increases via resistance and limits high-frequency performance 1,6.

The choice of adhesion system must balance hermeticity requirements, thermal budget constraints (glass substrates with low Tg ~550°C limit annealing temperatures), and manufacturing throughput (ALD MnOₓ deposition rates 0.5–1.5 Å/cycle vs. SAM functionalization batch processing) 2,6.

Electrochemical Copper Filling Strategies For High-Aspect-Ratio Through-Glass Vias

Hybrid Electroless-Electrolytic Plating Sequences For Void-Free Filling

Achieving void-free copper filling in through-glass via copper filled substrates with aspect ratios >5 and diameters <50 μm requires a two-stage plating strategy: (i) conformal electroless copper seed layer (0.5–2 μm) to ensure continuous conductivity along via sidewalls, followed by (ii) bottom-up electrolytic copper filling using suppressor-accelerator-leveler additive systems 3,9,10. The electroless seed layer deposition rate must be controlled at 1–2 μm/h to avoid premature via opening closure, which would trap voids in the via center 9.

Electrolytic copper plating employs acid sulfate baths (CuSO₄·5H₂O 200–250 g/L, H₂SO₄ 50–80 g/L) at 20–30°C with three-component additive packages: (i) suppressor (polyethylene glycol, MW 1000–8000, 50–200 ppm) adsorbs on field regions to reduce deposition rate, (ii) accelerator (bis(3-sulfopropyl) disulfide or mercaptopropanesulfonic acid, 1–10 ppm) accumulates in via bottoms to enhance local deposition, and (iii) leveler (quaternary ammonium compounds or Janus Green B, 0.5–5 ppm) preferentially inhibits deposition on convex features 4,13. Current density profiles typically start at 0.5–1 A/dm² for the first 30–50% of filling, then ramp to 2–5 A/dm² to accelerate field plating and minimize overburden 10.

Pulse-Reverse Electroplating For Stress Reduction And Grain Refinement

Pulse-reverse (PR) electroplating applies alternating forward (cathodic) and reverse (anodic) current pulses to control copper microstructure and reduce residual tensile stress in through-glass via copper filled substrates 1,5. Typical PR waveforms comprise: forward pulse 5–20 ms at 2–10 A/dm², reverse pulse 0.5–2 ms at 0.5–2 A/dm², with duty cycle 80–95% and frequency 50–200 Hz 5. The reverse pulse dissolves high-energy grain boundaries and surface protrusions, promoting (111) texture and reducing average grain size from 500–1000 nm (DC plating) to 100–300 nm (PR plating) as measured by electron backscatter diffraction (EBSD) 1.

Residual stress measurements by wafer curvature (Stoney equation) show that PR plating reduces tensile stress from 150–250 MPa (DC) to 50–100 MPa (PR), critical for preventing via extrusion during thermal cycling 5. The finer grain structure also improves electromigration resistance: median time to failure (MTF) at 150°C and 2×10⁶ A/cm² increases from 800 h (DC) to >2000 h (PR) per JEDEC JESD61 1. However, PR plating reduces deposition rate by 20–40% compared to DC, requiring optimization of pulse parameters to balance throughput and reliability 5.

Selective Via Filling With Photoresist Masking To Minimize Overburden

Selective filling methods employ photoresist or dry-film masks on the glass substrate surface to confine copper deposition within vias, reducing overburden thickness from 10–30 μm (blanket plating) to <5 μm and simplifying subsequent chemical-mechanical polishing (CMP) 5. The process sequence comprises: (i) lamination of 15–30 μm dry-film photoresist, (ii) UV exposure and development to open via areas, (iii) electrolytic copper filling to 5–10 μm above the glass surface, (iv) photoresist stripping, and (v) CMP or wet etching to planarize the surface 5.

Blocking layer materials must withstand acidic copper plating baths (pH 0.5–1.5) and elevated temperatures (25–35°C) for 30–90 min plating duration without delamination or undercutting 5. Polyimide-based dry films with adhesion promoters (silane coupling agents) exhibit <2% dimensional change and <5 μm undercut after 60 min immersion in CuSO₄/H₂SO₄ electrolyte at 30°C 5. Post-plating CMP removal rates of 200–400 nm/min (using silica slurry, pH 10–11, 3–5 psi downforce) reduce overburden to <1 μm with <50 nm surface roughness (Ra), suitable for subsequent redistribution layer (RDL) patterning 1.

Thermal Stress Management And Hermetic Sealing In TGV Copper Filled Substrates

CTE Mismatch And Circumferential Cracking Mechanisms

The CTE mismatch between copper (αCu = 16.5 ppm/K) and borosilicate glass (αglass = 3.3 ppm/K) generates radial tensile stress in the glass surrounding copper-filled vias during cooling from processing temperatures 7. Finite element analysis (FEA) predicts maximum hoop stress σθ at the via sidewall:

σθ ≈ E_glass × (αCu - αglass) × ΔT / (1 - ν_glass)

where E_glass = 70 GPa, ν_glass = 0.2, and ΔT = 300 K (cooling from 350°C annealing to 25°C ambient) yields σθ ≈ 280 MPa, exceeding the fracture strength of pristine borosilicate glass (50–100 MPa) and initiating circumferential cracks 7. Crack propagation is driven by stress concentration at via corners (stress intensity factor K_I ∝ σθ√(πa), where a is the initial flaw size ~0.5–2 μm from laser drilling or wet etching) 7.

Partial Via Filling And Cavity Formation For Stress Relief

A stress-relief architecture employs partial copper filling to create controlled cavities that accommodate differential thermal expansion 7. The via is divided into three axial regions: (i) first axial portion (top 20–40% of via length) with conformal copper coating (thickness 3–12 μm) defining a first cavity, (ii) second axial portion (middle 20–60%) with complete copper filling, and (iii) third axial portion (bottom 20–40%) with conformal coating defining a second cavity 7. This geometry reduces peak hoop stress by 40–60% (FEA simulation) while maintaining electrical conductivity (DC resistance <10 mΩ for 100 μm diameter, 500 μm length via) and hermetic sealing at the filled region (helium leak rate <1×10⁻⁸ atm·cm³/s) 7.

The partial filling is achieved by controlling electrolytic plating duration and current density: initial plating at 1–2 A/dm² for 10–20 min deposits 3–8 μm conformal coating, followed by increased current density to 5–10 A/dm² for 30–60 min to preferentially fill the middle region via bottom-up mechanism, then reverting to 1–2 A/dm² for final top coating 7. Cavity dimensions are verified by cross-sectional scanning electron microscopy (SEM) and X-ray computed tomography (CT) with <5 μm resolution 7.

Helium Leak Testing And Hermeticity Qualification Standards

Hermetic sealing requirements for through-glass via copper filled substrates in RF filters and MEMS packaging mandate helium leak rates <1×10⁻⁸ atm·cm³/s per MI