Through Glass Via Core Substrate: Advanced Architectures And Manufacturing Strategies For High-Density Electronic Packaging

Fundamental Architecture And Structural Characteristics Of Through Glass Via Core Substrates

Through glass via (TGV) core substrates constitute a critical innovation in microelectronic packaging, wherein electrically conductive pathways penetrate through a glass core layer to establish vertical interconnections between integrated circuit (IC) dies and next-level assemblies such as printed circuit boards (PCBs) 1. The glass core typically comprises borosilicate or aluminosilicate glass with thickness ranging from 100 μm to 500 μm, selected for its low coefficient of thermal expansion (CTE) of 3–5 ppm/°C, high dielectric constant stability (εr ≈ 4.5–6.0 at 1 GHz), and excellent dimensional stability across thermal cycling 5. Build-up structures, consisting of multiple dielectric and metallization layers, are laminated on both sides of the glass core to form redistribution layers (RDLs) that route signals between the TGVs and surface-mounted components 1.

The TGV itself is formed by laser-assisted selective etching or mechanical drilling, creating openings with diameters typically between 20 μm and 150 μm and aspect ratios (depth-to-diameter) ranging from 5:1 to 10:1 2,16. These openings are subsequently metallized with copper (Cu) via electroplating, often preceded by deposition of a conductive seed layer or liner material to ensure uniform plating and adhesion 10. The resulting conductive vias provide low-resistance electrical paths (typically <10 mΩ per via) and support current densities exceeding 10^5 A/cm² under operational conditions 5.

Key structural features include:

• Glass Core Composition: Borosilicate or aluminosilicate glass with Young's modulus of 70–90 GPa, providing mechanical rigidity and resistance to warpage during thermal excursions 1,5.
• Via Geometry: Cylindrical or tapered profiles with sidewall roughness <1 μm Ra, critical for minimizing plating voids and ensuring reliable electrical continuity 12,14.
• Liner Materials: Carbon-based sidewall liners or porous oxide layers (e.g., SiO₂ with porosity 10–30%) deposited via atomic layer deposition (ALD) or chemical vapor deposition (CVD) to enhance adhesion and prevent copper diffusion into glass 5,10,12.
• Build-Up Layers: Alternating dielectric (e.g., polyimide, epoxy resin with εr ≈ 3.0–3.5) and copper metallization layers (thickness 5–20 μm per layer) fabricated using photolithography and semi-additive processes 1,4.

The integration of TGVs within glass cores enables first-level interconnect (FLI) bump pitch scaling, allowing die-to-substrate connections at pitches as fine as 40 μm, compared to 100–150 μm typical for organic core substrates 2. This pitch reduction directly translates to higher I/O density (>10,000 I/Os per cm²) and reduced substrate layer count, lowering manufacturing costs and improving signal integrity by shortening electrical path lengths 2.

Fabrication Processes And Manufacturing Methodologies For Through Glass Via Core Substrates

Laser-Assisted Selective Etching For Via Formation

The predominant method for TGV fabrication involves laser-induced modification of glass microstructure followed by selective chemical etching 1,16,19. A focused ultrafast laser (typically femtosecond or picosecond pulse duration, wavelength 1030–1064 nm) is scanned through the glass thickness, inducing localized phase transformation or densification in the irradiated regions 19. The modified glass exhibits enhanced etch selectivity (etch rate ratio of modified-to-unmodified glass ≈10:1 to 50:1) when immersed in hydrofluoric acid (HF) or potassium hydroxide (KOH) solutions 20.

For thick glass cores (>300 μm), dual-sided laser exposure is employed to ensure complete via formation, resulting in an hourglass-shaped cross-section with a narrower mid-plane region 16. This geometry poses challenges for subsequent metallization, as the constricted middle section increases the risk of plating voids and incomplete via filling 16. To mitigate this, advanced fabrication strategies include:

• Multi-Pass Laser Exposure: Sequential laser scans with varying focal depths and energy densities to achieve more uniform via profiles 19.
• Etch Rate Modulation: Adjusting HF concentration (5–20 wt%) and temperature (20–60°C) to control sidewall taper and surface roughness 20.
• Post-Etch Diameter Expansion: Immersing the glass substrate in HF-containing etchant after initial via formation to enlarge via diameter by 5–15 μm, reducing aspect ratio and facilitating plating 20.

Typical process parameters for laser-assisted TGV formation include laser pulse energy of 1–10 μJ, repetition rate of 100–500 kHz, and scan speed of 10–100 mm/s 19. Etching is performed in 10–15 wt% HF solution at 40–50°C for 30–90 minutes, achieving etch rates of 5–20 μm/min for modified glass 20.

Metallization And Seed Layer Deposition

Following via formation, a conductive seed layer is deposited on the via sidewalls to enable electroplating 10. Conventional sputtering techniques face limitations in high-aspect-ratio vias due to poor step coverage and shadowing effects 10. Alternative approaches include:

• Electrically Conductive Polymer Deposition: Oxidative chemical vapor deposition (oCVD) or initiated CVD (iCVD) of conjugated polymers (e.g., poly(3,4-ethylenedioxythiophene) or PEDOT) with electrical conductivity of 10²–10³ S/cm, providing conformal coating on via sidewalls with thickness uniformity >90% 10.
• Atomic Layer Deposition (ALD) Of Metal Oxides: Sequential deposition of titanium dioxide (TiO₂) or tantalum pentoxide (Ta₂O₅) followed by reduction to metallic Ti or Ta, forming a 5–20 nm seed layer with step coverage >95% 5,12.
• Porous Liner Integration: Deposition of porous silica (SiO₂) or carbon-based liners with controlled porosity (10–30%) to enhance adhesion and accommodate CTE mismatch between copper and glass (CTE of Cu ≈17 ppm/°C vs. glass ≈3–5 ppm/°C) 12.

Electroplating is performed in acidic copper sulfate baths (CuSO₄ concentration 50–200 g/L, H₂SO₄ concentration 50–150 g/L) at current densities of 1–5 A/dm² and temperatures of 20–30°C 5. Plating time ranges from 2 to 8 hours depending on via depth and desired copper thickness 5. Post-plating annealing at 150–250°C for 1–2 hours improves copper grain structure and reduces resistivity to <2 μΩ·cm 5.

Lamination And Build-Up Layer Fabrication

After via metallization, dielectric and copper layers are sequentially laminated onto both sides of the glass core to form RDLs 1,4. The lamination process involves:

• Dielectric Layer Application: Spin-coating or lamination of photosensitive polyimide or epoxy resin films (thickness 10–30 μm per layer) followed by UV exposure and thermal curing at 150–200°C for 1–2 hours 4.
• Via Opening And Metallization: Laser drilling or photolithographic patterning to create microvias (diameter 20–50 μm) connecting RDL layers, followed by copper electroplating 4.
• Surface Planarization: Chemical-mechanical polishing (CMP) to achieve surface roughness <50 nm Ra, ensuring reliable solder joint formation and die attachment 1.

For multi-layer glass core substrates, individual glass sections with pre-patterned TGVs are bonded using adhesive layers (e.g., epoxy or silicone-based bonding films with thickness 5–20 μm and glass transition temperature Tg >150°C) under pressure (0.5–2 MPa) and temperature (120–180°C) for 30–60 minutes 4,6,15. Alignment accuracy between bonded layers is maintained within ±5 μm using optical alignment marks and precision bonding equipment 16.

Electrical Performance And Signal Integrity Characteristics Of Through Glass Via Core Substrates

Low-Loss Signal Transmission And High-Frequency Performance

Glass core substrates with TGVs exhibit superior electrical performance compared to organic core substrates, particularly at high frequencies (>10 GHz) relevant to 5G communications, data center interconnects, and advanced computing applications 7. Key performance metrics include:

• Dielectric Loss Tangent: Glass cores demonstrate dissipation factor (tan δ) of 0.002–0.005 at 10 GHz, compared to 0.01–0.02 for organic laminates, resulting in 50–70% reduction in signal attenuation 7.
• Insertion Loss: TGV-based transmission lines exhibit insertion loss of 0.5–1.5 dB per cm at 20 GHz, enabling longer signal routing distances without repeaters or equalization 7.
• Crosstalk Reduction: The low dielectric constant and high resistivity (>10¹⁴ Ω·cm) of glass minimize capacitive and inductive coupling between adjacent signal lines, achieving crosstalk levels <-40 dB for 50 μm pitch traces 2,5.

For electro-optic applications, glass core substrates integrate optical waveguides and TGVs to route both optical and electrical signals within a single platform 7. High-index waveguides (e.g., silicon nitride or tantalum pentoxide with refractive index n ≈2.0–2.2) are embedded in the glass core, coupled to surface-mounted photonic devices via vertical optical vias or mirrors 7. This hybrid integration enables data transmission rates exceeding 100 Gbps per channel with power consumption <5 pJ/bit 7.

Thermal Management And Power Delivery

TGVs facilitate efficient power delivery to high-performance ICs by providing low-inductance current paths (inductance <10 pH per via) and enabling dense power distribution networks 2. The thermal conductivity of glass (1.0–1.4 W/m·K) is lower than that of silicon (150 W/m·K) or copper (400 W/m·K), necessitating integration of thermal vias or heat spreaders to manage heat dissipation 1. Strategies include:

• Copper-Filled Thermal Vias: Arrays of large-diameter TGVs (diameter 100–200 μm, pitch 200–500 μm) filled with copper to enhance vertical heat conduction, achieving effective thermal conductivity of 5–15 W/m·K for the composite substrate 1.
• Embedded Heat Spreaders: Integration of metal plates (e.g., copper or aluminum with thickness 100–300 μm) within the glass core or on the substrate backside to laterally distribute heat 1.
• Thermal Interface Materials (TIMs): Application of high-conductivity TIMs (thermal conductivity >5 W/m·K) between the die and substrate to minimize thermal resistance (<0.1 K·cm²/W) 1.

For power-hungry applications such as graphics processing units (GPUs) or artificial intelligence (AI) accelerators, TGV substrates support power delivery networks with current densities exceeding 1 A/mm² and voltage drop <50 mV across the substrate 2.

Applications And Industry-Specific Use Cases For Through Glass Via Core Substrates

High-Performance Computing And Data Center Infrastructure

TGV core substrates are increasingly adopted in high-performance computing (HPC) and data center applications, where they enable heterogeneous integration of multiple chiplets (e.g., CPU, GPU, memory, I/O controllers) on a single package substrate 2,11. Key advantages include:

• Reduced Substrate Layer Count: TGV-enabled bump pitch scaling allows direct die-to-substrate connections with fewer RDL layers (typically 4–6 layers vs. 8–12 layers for organic substrates), reducing manufacturing cost by 20–30% and improving yield 2.
• Enhanced Signal Integrity: Low-loss glass dielectric and short electrical path lengths minimize signal distortion and enable data rates exceeding 56 Gbps per lane (PAM4 modulation) for chip-to-chip communication 2,7.
• Improved Thermal Performance: Integration of thermal vias and heat spreaders within the glass core facilitates heat dissipation from high-power chiplets (power density >100 W/cm²), maintaining junction temperatures below 85°C under sustained operation 1.

A representative case study involves a multi-chiplet GPU package with four compute dies and two high-bandwidth memory (HBM) stacks mounted on a glass core substrate with >5,000 TGVs 11. The substrate achieved die-to-die interconnect pitch of 50 μm, enabling aggregate memory bandwidth of 2 TB/s and reducing package warpage to <50 μm across a 50 mm × 50 mm footprint 11.

Telecommunications And 5G/6G Infrastructure

In telecommunications infrastructure, TGV substrates support the integration of radio-frequency (RF) front-end modules, power amplifiers, and antenna arrays for 5G and emerging 6G systems 7. The low dielectric loss and high dimensional stability of glass cores are critical for maintaining signal integrity at millimeter-wave frequencies (24–100 GHz) 7. Specific applications include:

• Phased Array Antennas: Glass substrates with embedded TGVs and surface-mounted antenna elements enable beamforming and beam-steering capabilities with phase accuracy <5° and gain >20 dBi 7.
• RF Filters And Resonators: Integration of high-Q inductors and capacitors within the glass core using hollow cylindrical TGVs (Q-factor >50 at 10 GHz) for compact, low-loss filtering 18.
• Electro-Optic Modulators: Hybrid integration of thin-film lithium niobate (LiNbO₃) modulators with glass core substrates for optical signal modulation at data rates >100 Gbps, supporting long-haul fiber-optic communication and data center interconnects 7.

Field trials of 5G base stations employing TGV-based RF modules demonstrated 30% reduction in power consumption and 40% improvement in signal-to-noise ratio (SNR) compared to conventional organic substrates 7.

Automotive Electronics And Advanced Driver-Assistance Systems (ADAS)

Automotive applications demand substrates with exceptional reliability under harsh environmental conditions, including wide temperature ranges (-40°C to 150°C), high humidity (>85% RH), and mechanical vibration (>10 g acceleration) 13. TGV core substrates meet these requirements through:

• Thermal Stability: Glass cores exhibit minimal CTE mismatch with silicon dies (CTE of Si ≈2.6 ppm/°C), reducing thermomechanical stress and solder joint fatigue during thermal cycling (>1,000 cycles per AEC-Q100 Grade 0 qualification) 1,13.
• Chemical Resistance: Glass is inert to automotive fluids (e.g., coolants, oils, fuels) and resistant to corrosion, ensuring long-term reliability (>15 years operational lifetime) 13.
• High-Voltage Isolation: The high dielectric breakdown strength of glass (>10 MV/cm) enables safe operation of power electronics and battery management systems at voltages exceeding 800 V 13.

A case study of an ADAS sensor module integrated a radar transceiver, image processor, and power management IC on a glass core substrate with 2,000 TGVs 13. The module achieved operating temperature range of -40°C to 125°C, electromagnetic interference