Thick Glass Core Substrate: Advanced Architectures, Manufacturing Processes, And Applications In High-Performance Semiconductor Packaging

Structural Composition And Material Characteristics Of Thick Glass Core Substrates

Thick glass core substrates are engineered multi-layer assemblies designed to serve as the foundational platform for integrated circuit (IC) packaging. The core structure typically comprises one or more discrete glass layers with thicknesses ranging from 100 μm to over 500 μm, selected based on mechanical strength requirements and via aspect ratio constraints 23. These glass layers exhibit a coefficient of thermal expansion (CTE) in the range of 3.0–4.5 ppm/°C, closely matching that of silicon IC dies (approximately 2.6 ppm/°C), thereby minimizing thermomechanical stress during thermal cycling 13. The glass material provides a dielectric constant (Dk) typically between 4.5 and 6.5 at 1 GHz, significantly lower than organic laminates, which enhances signal propagation speed and reduces dielectric losses critical for high-frequency applications 17.

The structural integrity of thick glass core substrates is further enhanced through multi-layer lamination techniques. In advanced configurations, two or more discrete glass sections are bonded together using intermediate bonding layers composed of adhesive polymers or low-temperature glass frits 21012. These bonding layers, with thicknesses ranging from 5 μm to 50 μm, ensure mechanical cohesion while maintaining electrical isolation between conductive features. The bonded multi-layer glass core architecture allows for the integration of complex via structures and embedded passive components, such as capacitors formed within cavities in the glass layers 13.

Through-glass vias (TGVs) constitute the critical vertical interconnect elements in thick glass core substrates. These vias are formed by laser drilling, mechanical drilling, or wet/dry etching processes, creating holes with diameters typically between 20 μm and 150 μm and aspect ratios (depth-to-diameter) ranging from 3:1 to 10:1 1417. The via sidewalls often exhibit controlled nanoporosity gradients, with laser-treated areas showing higher nanoporosity (up to 15% porosity) compared to untreated glass regions (less than 2% porosity), which facilitates subsequent metallization adhesion 1. Conductive materials, primarily electroplated copper with seed layers of nickel (phosphorus content ≤5 mass%) or titanium/copper, fill the TGVs to establish electrical pathways between the top and bottom surfaces of the glass core 91719.

Build-up layers are deposited on both sides of the glass core to create multi-level wiring structures. These layers consist of alternating dielectric films (such as photosensitive polyimides or epoxy-based materials with thicknesses of 10–30 μm per layer) and patterned copper traces (5–20 μm thick) 31518. The build-up process enables fine-pitch redistribution of signals from the dense TGV array to larger-pitch solder ball or land grid array (LGA) pads on the substrate surface. Advanced designs incorporate up to 6–10 build-up layers on each side of the glass core, achieving line/space dimensions as fine as 2 μm/2 μm 15.

Manufacturing Processes And Fabrication Techniques For Thick Glass Core Substrates

Glass Core Preparation And Via Formation

The manufacturing of thick glass core substrates begins with the selection and preparation of high-purity borosilicate or aluminosilicate glass panels, typically supplied in large-format sizes (e.g., 510 mm × 515 mm or larger) to enable panel-level processing 20. The glass panels undergo surface treatment processes, including chemical mechanical polishing (CMP) to achieve surface roughness (Rq) values between 0.5 nm and 5 nm, which is critical for subsequent adhesion of seed layers and dielectric films 16. Surface roughness optimization follows the bond roughness index criterion: Rq × Rku² = 3.5–150 nm, where Rku represents kurtosis, ensuring uniform adhesion of electrically conductive layers while maintaining high-frequency signal transmission efficiency 16.

Via formation in thick glass cores employs multiple techniques depending on the required via diameter, aspect ratio, and throughput. Laser drilling using ultraviolet (UV) or infrared (IR) picosecond or femtosecond lasers is the predominant method for creating vias with diameters of 20–100 μm 14. The laser ablation process generates controlled micro-cracks extending 2–10 μm into the glass sidewalls, which are subsequently filled with conductive material to enhance electrical connectivity and mechanical anchoring 4. For larger-diameter vias (100–200 μm), mechanical drilling with diamond-coated bits or ultrasonic machining is employed, followed by wet chemical etching using hydrofluoric acid (HF) solutions (5–20% concentration) to smooth sidewall roughness and remove debris 317.

After via formation, the glass panels undergo desmear and cleaning processes involving sequential treatments with alkaline cleaners (pH 10–12), deionized water rinses, and plasma activation (oxygen or argon plasma at 100–300 W for 30–120 seconds) to remove organic residues and enhance surface wettability for metallization 919.

Metallization And Conductive Layer Deposition

Metallization of TGVs and surface pads is achieved through a multi-step electroless and electrolytic plating sequence. Initially, a thin seed layer (50–200 nm) of electroless nickel-phosphorus (Ni-P) or palladium (Pd) is deposited on the via sidewalls and glass surfaces 919. The Ni-P seed layer is formulated with phosphorus content ≤5 mass% to minimize brittleness and reduce susceptibility to cracking under thermal stress 9. This is followed by electroless copper deposition (0.5–2 μm thickness) to establish a continuous conductive base for subsequent electrolytic plating 19.

Electrolytic copper plating is performed in acidic copper sulfate baths (copper concentration 50–80 g/L, sulfuric acid 150–200 g/L) at current densities of 1–5 A/dm² and temperatures of 20–30°C, filling the vias and building up surface pads to thicknesses of 10–30 μm 917. The plating process is carefully controlled to avoid void formation within high-aspect-ratio vias, often employing pulse-reverse plating techniques or additives (suppressors, accelerators, levelers) to ensure complete via filling 1719.

In advanced architectures, a dielectric buffer layer (e.g., silicon dioxide, silicon nitride, or organic polymers with thicknesses of 0.1–2 μm) is deposited between the glass via sidewalls and the copper fill to mitigate CTE mismatch stress and prevent copper diffusion into the glass matrix 17. This buffer layer is applied via plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) prior to seed layer deposition, enhancing long-term reliability under thermal cycling (e.g., -40°C to +125°C, 1000+ cycles) 17.

Build-Up Layer Fabrication And Patterning

Build-up layers are sequentially laminated or spin-coated onto the metallized glass core surfaces. Photosensitive dielectric materials (e.g., photoimageable polyimides or epoxy-based dry films) are applied in thicknesses of 10–30 μm per layer, exposed using UV lithography (i-line 365 nm or broadband UV sources), and developed to create via openings and trench patterns for subsequent copper traces 31518. The photolithography process achieves feature resolutions down to 2 μm line width and 2 μm spacing, enabling high-density interconnects 15.

Copper traces in the build-up layers are formed by semi-additive processes (SAP) or modified semi-additive processes (mSAP). In SAP, a thin copper seed layer (0.3–1 μm) is sputtered or electrolessly deposited, followed by photoresist patterning, electrolytic copper plating (5–15 μm), resist stripping, and flash etching of the seed layer 1518. The mSAP variant employs thinner seed layers (50–200 nm) and more aggressive etching to achieve finer line/space dimensions 15.

Multiple build-up layers (typically 3–6 layers per side) are stacked iteratively, with each layer undergoing via drilling (laser or mechanical), desmear, metallization, and patterning steps 315. The final build-up structure is capped with a solder mask layer (10–30 μm thick epoxy-based material) patterned to expose solder ball pads or LGA contact areas 3.

Singulation And Edge Protection Strategies

Singulation of thick glass core substrates into individual package units presents significant challenges due to glass brittleness. Traditional dicing methods (mechanical sawing with diamond blades) can induce edge chipping, micro-cracks, and catastrophic fractures, particularly in thin glass cores (<300 μm) 120. To mitigate these issues, laser-assisted singulation techniques are employed, wherein laser scribing creates controlled stress concentration zones along the intended separation lines, followed by mechanical breaking or stealth dicing (internal laser modification) to achieve clean separation with minimal edge damage 1.

Hybrid substrate architectures incorporating organic polymer frames or copper-clad laminate (CCL) borders around the glass core provide mechanical reinforcement during processing and handling 20. These frames, with widths of 5–20 mm, are bonded to the glass core perimeter using adhesive layers (e.g., prepreg materials or thermosetting epoxies) and remain attached through panel-level processing steps, protecting the glass edges from impact and reducing yield losses 20. After singulation, the organic frame can be retained as part of the final package or removed via routing or laser cutting 20.

Mechanical And Electrical Performance Characteristics Of Thick Glass Core Substrates

Mechanical Strength And Stress Management

Thick glass core substrates exhibit high flexural strength (typically 50–150 MPa for as-received glass) and elastic modulus (60–80 GPa), providing superior stiffness compared to organic laminates (elastic modulus 15–25 GPa) 158. This high modulus minimizes substrate warpage during thermal processing and improves planarity for subsequent die attach and wire bonding operations 14. However, the brittle nature of glass necessitates careful stress management to prevent catastrophic failure.

Residual stress engineering is employed to enhance impact resistance and static load strength. In laminated glass core designs, the glass core layer is sandwiched between glass skin layers with lower CTE, inducing residual compressive stress (50–200 MPa) in the skin layers and residual tensile stress (20–80 MPa) in the core 58. The relative thickness of skin layers (typically 10–30% of total substrate thickness) is optimized to maximize compressive stress in the skins while maintaining core tensile stress below the critical threshold for scribing and separation (approximately 100 MPa) 58. Intermediate interlayers with tailored CTE values can further modulate the stress distribution, reducing core tensile stress and enhancing overall substrate robustness 58.

Compressive stress vectors applied by overlying build-up layers during lamination and curing can induce defects, particularly at panel edges 14. Stress mitigation architectures incorporate buffer zones, such as reduced build-up layer thickness near panel perimeters, or the use of low-modulus adhesive layers between the glass core and build-up structures, to distribute stress more uniformly and prevent edge cracking 14.

Electrical Performance And Signal Integrity

Thick glass core substrates deliver exceptional electrical performance for high-frequency and high-speed applications. The low dielectric constant (Dk = 4.5–6.5) and low dissipation factor (Df = 0.002–0.008 at 1 GHz) of glass minimize signal attenuation and crosstalk, enabling data transmission rates exceeding 56 Gbps per lane (e.g., PCIe Gen 5, USB4) 17. The smooth glass surface (Rq < 5 nm) reduces conductor surface roughness losses, further improving signal integrity at millimeter-wave frequencies (>30 GHz) 16.

Through-glass vias exhibit low parasitic capacitance (0.05–0.2 pF per via, depending on via diameter and glass thickness) and inductance (10–50 pH per via), facilitating high-density vertical interconnects with minimal signal degradation 17. The incorporation of dielectric buffer layers between copper vias and glass sidewalls reduces capacitive coupling and enhances impedance control, critical for differential signaling applications 17.

The high thermal stability of glass (glass transition temperature Tg > 500°C for borosilicate compositions) ensures stable electrical properties over the operating temperature range of semiconductor devices (-40°C to +125°C), with minimal variation in Dk and Df 317. This thermal stability also supports high-temperature processing steps (e.g., solder reflow at 260°C) without degradation of substrate electrical performance 3.

Applications Of Thick Glass Core Substrates In Advanced Semiconductor Packaging

High-Performance Computing And Data Center Processors

Thick glass core substrates are increasingly adopted in high-performance computing (HPC) and data center processor packages, where they enable the integration of multiple high-bandwidth memory (HBM) stacks, chiplets, and I/O dies on a single substrate 2615. The low CTE of glass minimizes thermomechanical stress on silicon dies and solder joints during power cycling, enhancing package reliability over 10+ years of data center operation 23. The high via density achievable with TGVs (via pitch down to 40 μm) supports fine-pitch redistribution for HBM interfaces (1024+ I/O per stack) and die-to-die interconnects in chiplet architectures 15.

In heterogeneous integration scenarios, thick glass core substrates serve as the base for silicon bridge interposers embedded within cavities in the glass core 6. This hybrid architecture combines the high-density interconnect capability of silicon bridges (line/space down to 0.4 μm/0.4 μm) with the large-area, low-cost advantages of glass cores, enabling cost-effective scaling of multi-die packages 6. The glass core provides mechanical support and global power/ground distribution, while the silicon bridge handles ultra-fine-pitch chip-to-chip communication 6.

Typical performance metrics for HPC packages on thick glass core substrates include power delivery network (PDN) impedance <1 mΩ at 1 GHz, signal loss <1 dB per cm at 28 GHz, and substrate warpage <50 μm over a 60 mm × 60 mm package area after reflow 1517. These specifications ensure reliable operation of processors with thermal design power (TDP) exceeding 400 W and memory bandwidth >1 TB/s 15.

Mobile And Consumer Electronics

In mobile and consumer electronics, thick glass core substrates enable ultra-thin package profiles (total package thickness <0.5 mm) while maintaining mechanical rigidity and electrical performance 311. The use of glass cores with thicknesses of 100–200 μm, combined with thin build-up layers (total build-up thickness <100 μm per side), supports the miniaturization demands of smartphones, tablets, and wearable devices 311.

Land grid array (LGA) notch designs, wherein localized notches are formed through the glass core and build-up layers to accommodate LGA contact pads, facilitate low-profile socket-based connections for modular device architectures 11. These notches, with depths of 50–150 μm and widths of 200–500 μm, are created by laser ablation or mechanical milling and filled with buffer materials (e.g., organic polymers or elastomers) to prevent stress concentration during socket insertion 11.

The high thermal conductivity of glass (1.0–1.4 W/m·K for borosilicate compositions) aids in heat dissipation from mobile processors, complementing thermal interface materials (TIMs) and heat spreaders to maintain junction temperatures below 85°C under peak load conditions 3. The dimensional stability of glass cores (CTE mismatch <1 ppm/°C relative to silicon) ensures reliable solder joint integrity over 5000+ thermal cycles (-20°C to +85°C