Back-contact solar cell structure and manufacturing process thereof

Abstract

The present invention relates to the technical field of photovoltaic cells and specifically discloses a back-contact solar cell structure and a manufacturing process thereof, comprising: a silicon wafer, wherein a textured surface and a polished surface are alternately provided on the back surface of the silicon wafer; a P-type doped region is formed on the textured surface; a tunneling oxide layer and intrinsic polysilicon are deposited over the entire surface of the P-type doped region and the polished surface; the intrinsic polysilicon locally or entirely forms an N-type doped region at positions corresponding to the polished surfaces; a semiconductor layer is formed on the intrinsic polysilicon and the N-type doped region; and a P electrode and an N electrode are formed on the semiconductor layer. The present invention uniquely utilizes the deposition of intrinsic polysilicon on the back surface to simultaneously passivate the P-type and N-type regions, offering a simple and low-cost process.

Description

BACK-CONTACT SOLAR CELL STRUCTURE AND MANUFACTURING PROCESS THEREOF TECHNICAL FIELDThe present invention relates to the technical field of photovoltaic cells and specifically discloses a back-contact solar cell structure and a manufacturing process thereof. BACKGROUND TECHNOLOGY OF THE PRESENT INVENTIONExisting back-contact solar cells require two or more photolithography and etching processes to form P-type and N-type regions; consequently, their manufacturing costs are higher compared with other technologies (such as PERC or TopCon). Furthermore, TopCon and other manufacturing process flows are subject to numerous limitations when applied to existing production lines. While TBC (TopCon Back-Contact) structures have higher efficiency, they require photolithography, masking and etching processes to form N-type and P-type polysilicon layers as well as the tunneling silicon oxide (SiO2). Additionally, laser process is required to control current leakage problem at the P-type and N-type contact areas.In patent application US2023 / 0307573 A1, a tunneling oxide film and N-type polysilicon are applied to the N-type emitter based on P-type silicon wafer, while the P-type BSF is formed through the sintering process of aluminum electrodes. This technology is applicable only to P-type silicon wafers, and the use of Al2O3 imposes limitations on the passivation of the front and back surfaces. Moreover, the use of aluminum for the P electrode and silver for the N electrode presents drawbacks regarding material cost control.With regard to the aforementioned deficiencies of existing back-contact solar cells, there is an urgent need for a solution of back-contact solar cells with low-cost and high-efficiency, aiming to maximize the utilization of process equipment and process flows of existing TopCon production lines while reducing the manufacturing costs. SUMMARY OF THE PRESENT INVENTIONThe objective of the present invention is to overcome the shortcomings of the prior art and provide a back-contact solar cell structure and a manufacturing process thereof. In one aspect, the present invention discloses a back-contact solar cell structure, employing the following technical schemes. A back-contact solar cell structure and a manufacturing process thereof, comprising: a silicon wafer, wherein a textured surface and a polished surface are alternately provided on the back surface of the silicon wafer; a P-type doped region is formed on the textured surface; a tunneling oxide layer and intrinsic polysilicon are deposited over the entire surface of the P-type doped region and the polished surface; the intrinsic polysilicon locally or entirely forms an N-type doped region at positions corresponding to the polished surfaces; a semiconductor layer is formed on the intrinsic polysilicon and the N-type doped region; and a P electrode and an N electrode are formed on the semiconductor layer.Preferably, the N electrode is in direct contact with the semiconductor layer located on the N-type doped region, and the P electrode is in contact with the semiconductor layer located on the P-type doped region and / or in contact with the P-type doped region. Preferably, the N electrode and / or P electrode are formed of aluminium paste in which the silicon component content is 0 to 20 wt%. Preferably, the thickness of the tunneling oxide layer is 1 to 2 nm, the thickness of the intrinsic polysilicon is 50 to 300 nm, and the thickness of the semiconductor layer is 60 to 100 nm.Preferably, the material of the semiconductor layer is a single layer or a combination of multiple layers of TiO₂, WO₃, MoO₃, TeO₂, NiO, or TiN; the semiconductor layer contains a dopant, and the dopant content is 0 to 5 wt%; and the dopant includes one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).Preferably, an Al₂O₃ layer and an anti-reflective coating are sequentially formed on the front surface of the silicon wafer.Preferably, the thickness of the Al₂O₃ layer is 6 to 10 nm; the anti-reflective coating is a multilayer film composed of SiNx or SiNx / SiOx; and the thickness of the anti-reflective coating is 15 to 90 nm for SiNx, or 15 to 60 nm / 30 to 100 nm for SiNx / SiOx. In another aspect, the present invention discloses a manufacturing process for a back-contact solar cell structure, employing the following technical scheme.A manufacturing process for a back-contact solar cell structure, comprising the following steps:S1: forming a P-type doped region: texturing the back surface of a silicon wafer to form a textured surface, and performing boron-doped diffusion on the textured surface to form a P-type doped region;S2: locally forming a polished surface: performing localized laser and wet etching on the P-type doped region to form a polished surface, so that to partially expose the back surface of the silicon wafer;S3: forming a tunneling oxide layer and intrinsic polysilicon: depositing a tunneling oxide layer and intrinsic polysilicon over the entire surface of the P-type doped region and the polished surface;S4: forming an N-type doped region: printing locally or entirely over the intrinsic polysilicon at positions corresponding to the polished surfaces using a phosphorus-containing paste to form an N-type doped region; performing thermal treatment after the printing paste drying, so that phosphorus in the paste diffuses into the intrinsic polysilicon to form phosphorus-doped polysilicon;S5: forming a semiconductor layer: removing oxide films and paste residues from the surface, and then depositing a semiconductor layer locally or entirely over the intrinsic polysilicon and the N-type doped region; andS6: sintering the printing paste to form electrodes: sintering the printing paste on the semiconductor layer to form a P electrode and an N electrode, wherein the N electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P electrode is in contact with the semiconductor layer on the P-type doped region and / or in contact with the P-type doped region. Preferably, in the step S1, the boron doping concentration of the p-type doped region is 1E19 / cm³.Preferably, in the step S2, performing localized laser on the p-type doped region to remove BSG and the boron doping, wherein the laser pulse duration ranges from picosecond to continuous wave, and the laser energy density ranges from 0.5 J / cm² to 10 J / cm²; then, wet etching is performed by using an alkaline solution at a temperature above 45℃ to remove the laser loss in the laser processed region and the boron doping; a polished surface is formed by localized laser and wet etching , so that to expose a portion of the silicon wafer, with the exposed portion having a flat surface morphology.Preferably, in the step S3, the tunneling oxide layer is formed via an LPCVD process, a wet process or a thermal diffusion process, and the intrinsic polysilicon is formed via an LPCVD, APCVD, PVD or PECVD process.Preferably, in the step S4, the phosphorus content in the phosphorus paste is 1E19 / cm³ to 1E21 / cm³; after drying, the printing paste is placed into a diffusion furnace for a thermal treatment, at a diffusion temperature between 840℃ and 920℃, using nitrogen gas or oxygen-containing nitrogen gas.Preferably, in the step S5, after annealing, oxide films and paste residues are removed from the surface via wet etching; subsequently, Al₂O₃ and an anti-reflective coating are deposited on the front surface of the silicon wafer via an ALD process; a semiconductor layer is deposited on the back surface via a PVD, PECVD, APCVD, LPCVD or ALD process, with hydrogenation treatment performed using hydrogen gas and NH₃ during deposition.Preferably, in the step S6, the paste is an aluminium paste, the silicon content in the aluminium paste is 0 to 20 wt%, and the sintering temperature is between 860℃ and 920℃.Preferably, in the step S6, localized laser is performed on the deposited tunneling oxide layer and intrinsic polysilicon to form contact holes connected to the P-type doped region; then, the paste is printed and sintered to form a P electrode, and the P electrode is incontact with the P-type doped region.Compared with the prior art, the present invention at least has the following beneficial effects:1. Polysilicon is passivated simultaneously in P-type and N-type doped regions: The present invention specifically utilizes the deposition of intrinsic polysilicon on the back surface for simultaneously passivation of the P-type and the N-type regions. The tunneling oxide layer and the intrinsic polysilicon form as a whole across both the P-type doped regions and N-type doped regions. While the intrinsic polysilicon remains over the P-type doped regions, the intrinsic polysilicon over the N-type doped regions is selectively doped with phosphorus to form phosphorus-doped polysilicon. This eliminates the need for the traditional AlOx process and additional patterning on the P-type region to achieve passivation of both P-type and N-type doped regions, thereby offering a simple and low-cost manufacturing process advantage;2. By forming the P-type doped region on the textured surface and then the N-type doped region on the etched polished surface, and covering the entire surface with a tunneling oxide layer and intrinsic polysilicon, so that good longitudinal isolation is achieved between the N-type doped regions and P-type doped regions, thereby having a longer leakage current path, it means increasing the length of the leakage current path can effectively eliminate current leakage caused by contact between the P-type and N-type doped regions, thereby improving the pseudocapacitance fill factor (pFF); 3. Use of low-cost metal electrodes: A semiconductor layer is simultaneously formed on the polysilicon based on the traditional electrode sintering process. Since the semiconductor layer can block aluminum (Al) from diffusing into the polysilicon and has good contact resistance with aluminum, thus low-cost aluminum electrodes can be used to replace traditional silver electrodes, and both P-type electrode and N-type electrode are replaced with aluminum material;4. Thickness of polysilicon is reduced: By depositing a semiconductor layer on the polysilicon, the N electrode contacts the semiconductor layer rather than the polysilicon layer. Compared with traditional designs where metal electrodes contact the polysilicon directly, the present invention allows to reduce thesilicon thickness of polysilicon while still ensuring to block metal diffusion; and5. Simplifying the manufacturing process: The complex manufacturing process for back-contact solar cell of traditional TBC structures () is simplified to reduce the manufacturing costs and maximize the utilization of process equipment and process sequences of TopCon production lines, so that to converse the existing TopCon production lines to back-contact solar cell production lines in the future. BRIEF DESCRIPTION OF THE DRAWINGSFig. 1 is a schematic diagram of the overall structure of the back-contact solar cell structure according to Embodiment 1;Fig. 2 is a schematic diagram illustrating steps S1-S2 of the manufacturing process for the back-contact solar cell structure according to Embodiment 1;Fig. 3 is a schematic diagram illustrating step S3 of the manufacturing process for the back-contact solar cell structure according to Embodiment 1;Fig. 4 is a schematic diagram illustrating step S4 of the manufacturing process for the back-contact solar cell structure according to Embodiment 1;Fig. 5 is a schematic diagram illustrating step S5 of the manufacturing process for the back-contact solar cell structure according to Embodiment 1;Fig. 6 is a schematic diagram illustrating step S6 of the manufacturing process for the back-contact solar cell structure according to Embodiment 1;Fig. 7 is a flowchart of the manufacturing process for the back-contact solar cell structure according to Embodiment 1, where (a) shows the process flow of the present invention and (b) shows the existing TopCon process flow;Fig. 8 is a chart comparing open-circuit voltages for different materials used in the back-contact solar cell structure according to Embodiment 1;Fig. 9 is a schematic diagram illustrating step S6 of the manufacturing process for the back-contact solar cell structure according to Embodiment 4; andFig. 10 is a chart comparing the performance according to Embodiment 1 and Embodiment 4.Reference numerals:1: anti-reflective coating; 2: Al2O3; 3: P-type boron-doped region; 4: tunneling oxide layer; 5: N-type doped region; 6: intrinsic polysilicon; 7: semiconductor layer; 8: metal electrode; 9: phosphorus paste. DETAILED DESCRIPTION OF EMBODIMENTSTo make the objectives, features and advantages of the present invention more apparent and easily understood, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.Embodiment 1In this embodiment, referring to Fig. 1, a back-contact solar cell structure comprising: a silicon wafer, wherein a textured surface and a polished surface are alternately provided on the back surface of the silicon wafer; a P-type doped region 3 is formed on the textured surface; a tunneling oxide layer 4 and intrinsic polysilicon 6 are deposited over the entire surface of the P-type doped region 3 and the polished surface; the intrinsic polysilicon 6 locally forms an N-type doped region at positions corresponding to the polished surfaces; a semiconductor layer 7 is formed on the intrinsic polysilicon 6 and the N-type doped region 5; and metal electrodes 8, i.e., the P electrode and the N electrode, are formed on the semiconductor layer.In this embodiment, referring to Figs. 2-6, a manufacturing process for the back-contact solar cell structure, comprising the following steps:S1: Forming a P-type doped region: texturing the back surface of a silicon wafer, and performing boron-doped diffusion on the textured back surface by using a conventional diffusion furnace to form a P-type doped region, wherein the boron doping concentration is 1E19 / cm³ , and the surface morphology of the P-type doped region is a textured surface.S2: Locally forming a polished surface: The localized BSG and boron doping are removed from the back surface of the silicon wafer using a laser, specifically using a green laser (the wavelength is 532 nm), the pulse duration is 10 nsec and the laser energy density is 1.5 J / cm²); then, wet etching is performed by using an alkaline solution at a temperature above 45℃ to remove the laser loss in the laser processed region and the boron dopingon the front surface; localized laser and wet etching are performed to form a polished surface, so that to partially expose the back surface of the silicon wafer, with the exposed portion having a flat surface morphology, which distincts from the textured surface of the P-type doped region, as shown in Fig. 2.S3: Forming a tunneling oxide layer and intrinsic polysilicon: a tunneling oxide layer and intrinsic polysilicon are simultaneously formed via an LPCVD process, which entirely cover both the textured regions and the flat regions; the tunneling oxide layer has a thickness of approximately 1.2 nm, and the intrinsic polysilicon has a thickness of 50 nm; in addition to the LPCVD process, the intrinsic polysilicon may be formed via other deposition processes such as APCVD, PVD PECVD or etc., and the tunneling oxide layer may be formed via wet processs or other thermal diffusion processes, as shown in Fig. 3.S4: Forming a N-type doped region: printing phosphorus-containing paste onto the intrinsic polysilicon to form an N-type doped region; the phosphorus content in the phosphorus paste is approximately 1E20 / cm³, and the width of the printed area is less than the width of the laser-etched area (i.e., the width of the polished surface area), so that intrinsic polysilicon is reserved between the N-type doped region and the P-type doped region to serve as isolation and to prevent contact with the P-type doped region; after drying, the printing paste is placed into a diffusion furnace for a thermal treatment at a diffusion temperature of 920℃ using nitrogen gas or oxygen-containing nitrogen gas, causing the phosphorus in the paste to diffuse into the intrinsic polysilicon to form phosphorus-doped polysilicon, referring to Fig. 4.S5: Forming a semiconductor layer: After annealing, oxide films and paste residues are removed from the surface via wet etching; subsequently, Al₂O₃ and an anti-reflective coating are deposited on the front surface of the silicon wafer via an ALD process, with the Al₂O₃ layer having a deposition thickness of 8 nm and the anti-reflective coating (which is SiNx) having a thickness of 90 nm; a semiconductor layer is deposited on the back surface, the material of the semiconductor layer is TiO₂ and the deposition thickness of the semiconductor layer is 60 nm, using an LPCVD process, and PVD, PECVD, APCVD ALD or etc. may be alternatively used, and when depositing, hydrogen gas and NH₃ are used for hydrogenation treatment, referring to Fig. 5.S6: Sintering the printing paste to form electrodes: The printing paste is sintered on the semiconductor layer to form a P electrode and an N electrode, wherein the N electrode is in direct contact with the semiconductor layer on the N-type doped region, and the P electrode is in contact with the semiconductor layer on the P-type doped region. The paste is an aluminium paste with a silicon content of 0 wt%, and the sintering temperature is 920℃, referring to Fig. 6.In the present invention, a p-type doped region is formed on the textured surface; the textured surface can effectively reduce reflectivity under illumination of light and enhance bifaciality. Furthermore, due to its larger surface area, the textured surface is easier to establish a larger contact area with the electrode. Unlike existing p-type polysilicon (approximately 1E20 / cm³) formed by contact passivationdirectly on the polysilicon, the p-type doped region of the present invention has a lower boron doping concentration (approximately 1E19 / cm³), which helps reduce leakage current.Additionally, a recessed flat surface is formed on the side of the textured surface via laser wet etching, and then a tunneling oxide layer and intrinsic polysilicon are deposited to form a localized n-type doped region. This special configuration ensures effective longitudinal isolation between the p-type doped region and the n-type doped region; the tunneling oxide layer and intrinsic polysilicon increase the leakage current path between the p-type doped region and the n-type doped region, thereby enabling better control of leakage current.Fig. 7 illustrates the process flow of the technology proposed in the present invention. The present invention offers the advantage of compatibility with the process equipment and process flows of existing TOPCon production lines, making future upgrades to back-contact solar cell production lines straightforward and eliminating the need for additional process steps. Moreover, as existing production lines can be utilized directly, there is no need to expand the facility's footprint. Furthermore, since aluminum can be used as the electrode material for both p-type and n-type doped regions, there is a significant reduction in electrode material costs compared with PERC (which uses aluminum only on the back surface) or TOPCon (which uses silver on both the front and back surfaces).Fig. 8 demonstrates the passivation characteristics of the intrinsic polysilicon proposed for the silicon wafer in the present invention. In the present invention, the p-type region is formed by boron diffusion within the silicon wafer via existing process, while the n-type region employs a passivation contact of the tunneling oxide layer and intrinsic polysilicon, especially, passivation of the p-type region can be achieved using intrinsic polysilicon and bypassing the AlOx process; as shown in the drawing, the intrinsic polysilicon exhibits excellent passivation characteristics comparable to that of Al₂O₃ and even superior passivation quality than that of SiNx itself. This indicates that grain boundaries within the polysilicon can readily accommodate a large amount of hydrogen, which effectively passivates defects at the interface between the intrinsic polysilicon and the chip.Embodiment 2This embodiment differs from Embodiment 1 in that, in the step S5, a semiconductor layer 7 is formed on the back surface via deposition, and the material of the semiconductor layer 7 is WO3.Embodiment 3This embodiment differs from Embodiment 1 in that, in the step S5, a semiconductor layer 7 is formed on the back surface via deposition; the semiconductor layer 7 is a dual-layer structure including a first semiconductor layer and a second semiconductor layer sequentially from the silicon wafer outward,. In the step S5, the first semiconductor layer is first deposited on the back surface using TiO₂ with a deposition thickness of 50 nm; subsequently, the second semiconductor layer is deposited onto the first semiconductor layer using WO₃ with a deposition thickness of 40 nm.Embodiment 4This embodiment differs from Embodiment 1 in that, as shown in Fig. 9, in the step S6, prior to the metallization process, localized laser process is performed on the deposited tunneling oxide layer and intrinsic polysilicon to form contact holes connecting the P-type doped region, the wavelength of the laser is 355 nm, the pulse duration is 10 psec and the energy density range is 0.3-1.0 J / cm². The energy density may be adjusted based on the surface structure and its reflectivity. In other embodiments, the contact holes may be formed using other lasers, such as a green laser with a pulse duration of nanoseconds. After forming the contact holes via localized laser process, the printed aluminium paste is sintered to form a P electrode which contacts with the P-type doped region 3.Unlike Embodiment 1 where the metal electrode 8 contacts with the semiconductor layer 7, the metal electrode 8 directly contacts with the P-type doped region 3 in Embodiment 4, during the sintering process, the aluminium electrode reacts with the silicon to form aluminum-doped silicon (P-type doping) in the contact area (referring to Fig. 10), thereby improving the contact characteristics and reducing the contact resistance while ensuring that the line resistance does not become excessively high.The technical schemes provided by the present invention have been described in detail above, and specific examples have been used to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are intended solely to facilitate the understanding of the method and core concepts of the present invention. Furthermore, those skilled in the art may make modifications to the specific implementations and application scopes based on the concepts of the present invention. Therefore, the content of this specification should not be construed as limiting the present invention. 

Claims

1. A back-contact solar cell structure, comprising: a silicon wafer, wherein a textured surface and a polished surface are alternately provided on the back surface of the silicon wafer; a P-type doped region (3) is formed on the textured surface; a tunneling oxide layer (4) and intrinsic polysilicon (6) are deposited over the entire surface of the P-type doped region (3) and the polished surface; the intrinsic polysilicon (6) locally or entirely forms an N-type doped region (5) at positions corresponding to the polished surfaces; a semiconductor layer (7) is formed on the intrinsic polysilicon (6) and the N-type doped region (5); and a P electrode and an N electrode are formed on the semiconductor layer (7).

2. The back-contact solar cell structure according to claim 1, wherein the N electrode is in direct contact with the semiconductor layer (7) located on the N-type doped region (5), and the P electrode is in contact with the semiconductor layer (7) located on the P-type doped region (3) and / or in contact with the P-type doped region (3).

3. The back-contact solar cell structure according to claim 1, wherein the N electrode and / or P electrode are formed of an aluminium paste in which the silicon component content is 0 to 20 wt%.

4. The back-contact solar cell structure according to claim 1, wherein the thickness of the tunneling oxide layer (4) is 1 to 2 nm, the thickness of the intrinsic polysilicon (6) is 50 to 300 nm, and the thickness of the semiconductor layer (7) is 60 to 100 nm.

5. The back-contact solar cell structure according to claim 1, wherein the material of the semiconductor layer (7) is a single layer or a combination of multiple layers of TiO₂, WO₃, MoO₃, TeO₂, NiO, or TiN; the semiconductor layer (7) contains a dopant, and the dopant content is 0 to 5 wt%; and the dopant includes one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).

6. The back-contact solar cell structure according to claim 1, wherein an Al₂O₃ layer (2) and an anti-reflective coating (1) are sequentially formed on the front surface of the silicon wafer.

7. The back-contact solar cell structure according to claim 6, wherein the thickness of the Al₂O₃ layer (2) is 6 to 10 nm; the anti-reflective coating (1) is a multilayer film composed of SiNx or SiNx / SiOx; and the thickness of the anti-reflective coating (1) is 15 to 90 nm for SiNx, or 15 to 60 nm / 30 to 100 nm for SiNx / SiOx.

8. A manufacturing process for a back-contact solar cell structure according to any one of claims 1 to 7, comprising the following steps:S1: forming a P-type doped region (3): texturing the back surface of a silicon wafer to form a textured surface, and performing boron-doped diffusion on the textured surface to form a P-type doped region (3);S2: locally forming a polished surface: performing localized laser and wet etching on the P-type doped region (3) to form a polished surface, so that to partially expose the back surface of the silicon wafer;S3: forming a tunneling oxide layer (4) and intrinsic polysilicon (6): depositing a tunneling oxide layer (4) and intrinsic polysilicon (6) over the entire surface of the P-type doped region (3) and the polished surface;S4: forming an N-type doped region (5): printing locally or entirely over the intrinsic polysilicon (6) at positions corresponding to the polished surfaces using a phosphorus-containing paste (9) to form an N-type doped region (5); performing thermal treatment after the printing paste drying, so that phosphorus in the paste diffuses into the intrinsic polysilicon (6) to form phosphorus-doped polysilicon;S5: forming a semiconductor layer (7): removing oxide films and paste residues from the surface, and then depositing a semiconductor layer (7) locally or entirely over the intrinsic polysilicon (6) and the N-type doped region (5); andS6: sintering the printing paste to form electrodes: sintering the printing paste on the semiconductor layer (7) to form a P electrode and an N electrode, wherein the N electrode is in direct contact with the semiconductor layer (7) on the N-type doped region (5), and the P electrode is in contact with the semiconductor layer (7) on the P-type doped region (3) and / or in contact with the P-type doped region (3).

9. The manufacturing process for a back-contact solar cell structure according to claim 8, wherein, in the step S1, the boron doping concentration of the p-type doped region (3) is 1E19 / cm³;in the step S2, performing localized laser on the p-type doped region (3) to remove BSG and the boron doping, wherein the laser pulse duration ranges from picosecond to continuous wave, and the laser energy density ranges from 0.5 J / cm² to 10 J / cm²; then, wet etching is performed by using an alkaline solution at a temperature above 45℃ to remove the laser loss in the laser processed region and the boron doping; a polished surface is formed by localized laser and wet etching, so that to expose a portion of the silicon wafer, with the exposed portion having a flat surface morphology;in the step S3, the tunneling oxide layer (4) is formed via an LPCVD process, a wet process or a thermal diffusion process, and the intrinsic polysilicon (6) is formed via an LPCVD, APCVD, PVD or PECVD process;in the step S4, the phosphorus content in the phosphorus paste (9) is 1E19 / cm³ to 1E21 / cm³; after drying, the printing paste is placed into a diffusion furnace for thermal treatment, at a diffusion temperature between 840℃ and 920℃, using nitrogen gas or oxygen-containing nitrogen gas;in the step S5, after annealing, oxide films and paste residues are removed from the surface via wet etching; subsequently, Al₂O₃ (2) and an anti-reflective coating (1) are deposited on the front surface of the silicon wafer via an ALD process; a semiconductor layer (7) is deposited on the back surface via a PVD, PECVD, APCVD, LPCVD or ALD process, with hydrogenation treatment performed using hydrogen gas and NH₃ during deposition; andin the step S6, the paste is an aluminium paste, the silicon content in the aluminium paste is 0 to 20 wt%, and the sintering temperature is between 860℃ and 920℃.

10. The manufacturing process for a back-contact solar cell structure according to claim 9, wherein, in the step S6, localized laser is performed on the deposited tunneling oxide layer (4) and intrinsic polysilicon (6) to form contact holes connected to the P-type doped region (3); then, the paste is printed and sintered to form a P electrode, and the P electrode is in contact with the P-type doped region (3). 

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