Low-cost and high-performance solar cell and manufacturing process therefor

Abstract

A low-cost and high-performance solar cell and a manufacturing process therefor, the solar cell comprising: a silicon wafer, a tunneling oxide layer formed on the silicon wafer and a doped polysilicon, wherein an N-type doped region and a P-type doped region are formed on the doped polysilicon, and there is intrinsic polysilicon in a gap between the N-type doped region and the P-type doped region; a semiconductor layer is formed on the doped polysilicon, and the material of the semiconductor layer comprises one layer or a combination of layers of TiO2, WO3, MoO3, TeO2 or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doped region, a P-type electrode is formed on the semiconductor layer corresponding to the P-type doped region, and the N-type electrode and the P-type electrode come into contact with the semiconductor layer. The low-cost and high-performance solar cell can use a low-cost metal paste and sinter same into an electrode, and has the advantages of low cost and high performance.

Description

A LOW-COST AND HIGH-PERFORMANCE SOLAR CELL AND MANUFACTURING PROCESS THEREOF TECHNICAL FIELDThe present invention relates to the technical field of photovoltaic cells and specifically discloses a low-cost and high-performance solar cell and manufacturing process thereof. BACKGROUNDTECHNOLOGY OF THE PRESENT INVENTIONDuring the commercialization of the solar cell technologies, reducing costs while increasing efficiency has consistently been one of the most important objectives. The solar cell technologies generally utilize silver pastes and rapid sintering processes to form electrodes. Since silver paste has excellent chemical stability and high electrical conductivity of silver, as well as lower contact resistancee with silicon, it is still used as the electrode material in most solar cell technologies so far. However, the high cost of silver increases the overall cost of solar cells.To address this issue, various electrode formation technologies utilizing non-noble metal materials have been proposed. For instance, Patent US9293624B2 introduced a technology for electroplating copper electrodes, while Patent WO2012 / 047404 disclosed a method for forming copper electrodes via a plating process. Patent US9293624B2 has a need to form contact holes and apply mask to prevent plating issues of the electrode material onto non-electrode forming areas via technology of copper-plated electrodes. Furthermore, protective layers must be coated above and below to prevent copper diffusion, resulting in a more complex process and increased additional costs. In Patent WO2012 / 047404 coating the copper paste, the cost reduction effect is not significant due to still partial use of silver; and due to the oxidization of copper, only low-temperature sintering processes can be employed. Consequently, compared with high-temperature sintering processes, copper electrodes exhibit higher electrical resistance under the same electrode design.At present, except the PERC technology, most high-efficiency solar cell technologies (such as HJT, TopCon and IBC) still utilize silver electrodes; even for the PERC solar cell technology, the aluminum paste is used only for P-type electrodes on the back surface, the cost reduction effect is limited. For N-type electrodes, the reaction between aluminum and silicon creates P-type doping, which making it difficult to apply.For back-contact solar cells using P-type silicon wafers, Patent US2023 / 0307573A1 described a back-contact solar cell manufacturing technology similar to the PERC technology, i.e. silver paste is used for N-type electrodes and aluminum paste is used for P-type electrodes. However, when it (US2023 / 0307573A1) is applied to back-contact solar cell structures based on P-type silicon wafers, which is similar to PERC technology with aluminum used for P-type electrodes while silver still used for N-type electrodes, its application is limited. It can be seen, for these existing technologies, silver paste cannot be replaced fully, and the partial use of silver paste cannot effectively reduce overall silver consumption.To address the shortcomings of the aforementioned existing technologies, there is an urgent need for a novel low-cost and high-performance solar cell. SUMMARY OF THE PRESENT INVENTIONThe objective of the present invention is to overcome the shortcomings of the prior art by providing a low-cost and high-performance solar cell and a manufacturing process thereof. In one aspect, the present invention discloses a low-cost and high-performance solar cell, employing the following technical scheme.A low-cost and high-performance solar cell and manufacturing process thereof comprises a silicon wafer, and a tunneling oxide layer and doped polysilicon formed on the silicon wafer, wherein an N-type doped region and a P-type doped region are formed on the doped polysilicon, with intrinsic polysilicon spacing apart the N-type doped region and the P-type doped region; a semiconductor layer is formed on the doped polysilicon and the intrinsic polysilicon, and the materials of the semiconductor layer comprise a single layer or a combination of multiple layers of TiO2, WO3, MoO3, TeO2, or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doped region, and a P-type electrode is formed on the semiconductor layer corresponding to the P-type doped region, with the N-type electrode and the P-type electrode being in contact with the semiconductor layer. Preferably, the thickness of the doped polysilicon is 20 nm to 100 nm, and the thickness of the semiconductor layer is 10 nm to 100 nm. Preferably, the semiconductor layer above the P-type doped region has the same thickness as, or a smaller thickness than, the semiconductor layer above the N-type doped region.Preferably, the thickness of the semiconductor layer above the N-type doped region is 40 to 70 nm, and the thickness of the semiconductor layer above the P-type doped region is 20 to 70 nm.Preferably, a metal alloy is formed at the interface between the semiconductor layer and the P-type electrode and / or the N-type electrode.Preferably, the semiconductor layer contains 0 to 5 wt% of dopant, and the dopant comprises one or more of aluminium (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).Preferably, the P-type electrode and / or the N-type electrode contains Al, Ag, Cu, or a mixture thereof.Preferably, the P-type electrode and / or the N-type electrode are formed from an aluminium paste, and the silicon content in the aluminium paste is 0 to 20 wt%.Preferably, it further comprises a passivation layer.Preferably, the passivation layer is formed on the semiconductor layer.Preferably, the passivation layer is formed on the doped polysilicon and the intrinsic polysilicon; the semiconductor layer is formed on the passivation layer; the semiconductor layer extends through the passivation layer to be in contact with the doped polysilicon.Preferably, the materials of the passivation layer is a single layer or a combination of multiple layers of SiNx, SiOx, SiONx or Al2O3.In another aspect, the present invention discloses a manufacturing process for the low-cost and high-performance solar cell, employing the following technical scheme.A manufacturing process for the low-cost and high-performance solar cell, comprising the following steps:S1: forming a tunneling oxide layer and intrinsic polysilicon on a silicon wafer;S2: selectively implanting boron and phosphorus into the intrinsic polysilicon to form doped polysilicon, wherein N-type doped regions and P-type doped regions are alternately formed on the doped polysilicon, and intrinsic polysilicon is reserved between the N-type doped regions and the P-type doped regions to serve as isolation;S3: forming a semiconductor layer on the doped polysilicon; andS4: forming an N-type electrode and a P-type electrode on the semiconductor layer, so that the N-type electrode is in contact with the semiconductor layer above the N-type doped regions and the P-type electrode is in contact with the semiconductor layer above the P-type doped regions.Preferably, in the step S2, boron and phosphorus are selectively implanted via ion implantation, printing and thermal treatment of doped paste, or the use of a mask and a doping diffusion furnace.Preferably, in the step S3, the semiconductor layer over the P-type doped region is subjected to laser ablation treatment, or a metal alloy is formed on the semiconductor layer over the P-type doped region, so that the thickness of the semiconductor layer over the P-type doped region is less than that of the semiconductor layer over the N-type doped region.Preferably, in the step S4, the N-type electrode and the P-type electrode are simultaneously formed by printing and sintering a metal paste on the semiconductor layer, or the N-type electrode and the P-type electrode are separately formed by printing and sintering a metal paste on the semiconductor layer.Compared with the prior art, the present invention at least has the following beneficial effects:1. Application of low-cost electrode pastes: When traditional N-type polysilicon uses aluminium paste to form electrodes, there exists issues of P-type doping caused by the reaction between aluminum and polysilicon, or degradation in passivation characteristic caused by diffusion of aluminium into polysilicon. In the present invention, a semiconductor layer is used to block diffusion of aluminium into polysilicon while maintaining good contact resistance with aluminium. Consequently, low-cost metal electrodes, such as aluminium, can be employed.2. Reduction of polysilicon thickness: When traditional metal electrodes directly contact with polysilicon, it is difficult to reduce the thickness of polysilicon due to metal ion diffusion and peak problems, thus it is necessary to make the thickness remain above a certain value. Consequently, it is difficult to reduce parasitic absorption of light by the thick polysilicon layer—a particular constraint on improving bifaciality, especially in low-current scenarios on the back surface. In the present invention, by the structure forming a semiconductor layer over the doped polysilicon, the metal electrode contacts with the semiconductor layer rather than the underlying doped polysilicon. This allows for a reduction in polysilicon thickness and resolves the aforementioned issues. Furthermore, the semiconductor layer possesses a wide band gap, which can further minimize light absorption losses.3. Simplified manufacturing process: The semiconductor layer described herein can be fabricated using the same manufacturing processes employed for the doped polysilicon. It is compatible with low-temperature processing yet exhibits high-temperature stability, ensuring it remains unaffected during subsequent high-temperature steps; thus, it can be fabricated based on existing solar cell manufacturing processes without requiring additional processing steps. BRIEF DESCRIPTION OF THE DRAWINGSFig. 1 is a schematic structural diagram of the low-cost and high-performance solar cell of Embodiments 1-3;Fig. 2 is a schematic diagram illustrating step S1 of the manufacturing process for the low-cost and high-performance solar cell of Embodiment 1;Fig. 3 is a schematic diagram illustrating step S2 of the manufacturing process for the low-cost and high-performance solar cell of Embodiment 1;Fig. 4 is a schematic diagram illustrating step S3 of the manufacturing process for the low-cost and high-performance solar cell of Embodiment 1;Fig. 5 is a schematic diagram illustrating step S4 of the manufacturing process for the low-cost and high-performance solar cell of Embodiment 1;Fig. 6 is a schematic structural diagram of the low-cost and high-performance solar cell of Embodiment 4;Fig. 7 is a schematic diagram illustrating step S4 of the manufacturing process for the low-cost and high-performance solar cell of Embodiment 4;Fig. 8 is a schematic diagram illustrating an alternative manner for step S4 of the manufacturing process for the low-cost and high-performance solar cell of Embodiment 4;Fig. 9 is a graph showing the rear-side light reflectivity of different materials;Fig. 10 is a graph showing the rear-side light absorptivity of different materials;Fig. 11 is a graph showing the contact resistance characteristics with the aluminum electrode in the doped polysilicon and the semiconductor layer; andFig. 12 is a graph showing the PL intensity characteristics of photoluminescence detection of the doped polysilicon.Reference numerals:1: tunneling oxide layer; 2: intrinsic polysilicon; 3: P-type doped region; 4: N-type doped region; 5: semiconductor layer; 6: passivation layer; 7: P-type electrode; 8: N-type electrode. DETAILED DESCRIPTION OF THE PRESENT INVENTIONTo make the objectives, features and advantages of the present invention more apparent and easily understood, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.The present invention is applied to a TBC structure utilizing a tunneling oxide layer and doped polysilicon; it aims to enable the technology to be implemented based on existing electrode sintering processes by directly employing conventional aluminium paste and sintering processes. In this patent, a semiconductor layer is utilized over both the P-type doped region and the N-type doped region to block aluminium diffusion, thereby enabling excellent metal contact for aluminium on both the P-type electrode and the N-type doped region. By using low-cost aluminium paste and conventional sintering processes to form electrodes, high-efficiency and low-cost solar cells are produced.Embodiment 1Referring to Fig. 1(a), in this embodiment, a low-cost and high-performance solar cell comprising: a silicon wafer; and a tunneling oxide layer 1, doped polysilicon, a semiconductor layer 5 and a passivation layer 6 formed sequentially on the silicon wafer. Wherein, a P-type doped region 3 and an N-type doped region 4 are formed on the doped polysilicon, with intrinsic polysilicon 2 spacing apart the P-type doped region 3 and the N-type doped region 4. The semiconductor layer 5 entirely covers the doped polysilicon and the intrinsic polysilicon, and the material of the semiconductor layer 5 is TiO₂. A P-type electrode 7 is formed on the semiconductor layer 5 corresponding to the P-type doped region 3, and an N-type electrode 8 is formed on the semiconductor layer 5 corresponding to the N-type doped region 4; the P-type electrode 7 and the N-type electrode 8 are in contact with the semiconductor layer 5.In this embodiment, referring to Figs. 2-5, a manufacturing process for the low-cost and high-performance solar cell comprising the following steps:S1: Forming a tunneling oxide layer and intrinsic polysilicon: Referring to Fig. 2, a tunneling oxide layer and intrinsic polysilicon are formed on the back surface of a silicon wafer. The tunneling oxide layer is formed by performing thermal treatment to the surface of the silicon wafer and has a thickness of 1 to 2 nm. The intrinsic polysilicon is formed via LPCVD deposition and has a thickness of 20 nm. Wherein, the tunneling oxide layer may be formed on the silicon wafer via oxidation in vacuum equipment or a wet process. The intrinsic polysilicon may be deposited using methods such as PVD or PECVD, implanted via a diffusion furnace or prepared using various other processes.S2: Forming doped polysilicon: Referring to Fig. 3, boron and phosphorus are selectively implanted into intrinsic polysilicon via the printing of doped pastes and thermal treatment, to form alternating P-type doped regions and N-type doped regions, with intrinsic polysilicon reserved between the N-type doped regions and the P-type doped regions to serve as isolation. In addition to being formed via the printing of doped pastes and thermal treatment, the doped polysilicon may also be formed via ion implantation or via the use of a mask and a doping diffusion furnace.S3: Forming a semiconductor layer: Referring to Fig. 4, TiO2 with a thickness of 60 nm is formed, as the semiconductor layer, over the doped polysilicon and intrinsic polysilicon via PVD deposition. Deposition processes for the subordinate semiconductor layer may be vacuum deposition methods such as PECVD or ALD, or a paste printing process. The semiconductor layer may be doped with other elements. The dopant may be one or more of aluminium (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N) and oxygen (O). The dopant content may be 0 to 5 wt%. The semiconductor layer may also be a dual-layer semiconductor layer combined with TiO2 / TiOx (Al-doped TiOx), TiO2 / WO3 or TiO2 / MoO3, which are sequentially outward from the doped polysilicon, such a dual-layer semiconductor layer offers lower energy loss during charge collection and lower light reflectivity.S4: Forming metal electrodes: Referring to Fig. 5, aluminium paste is printed onto the semiconductor layer over the P-type and N-type doped regions, followed by a rapid thermal treatment to form a P-type electrode and an N-type electrode; the P-type electrode and the N-type electrode are in direct contact with the semiconductor layer, but not in contact the underlying doped polysilicon. Depending on specific requirements, the P-type electrode and the N-type electrode may also be printed separately. The rapid thermal treatment temperature is set to 920°C, with a peak temperature range of 840 to 920°C. The aluminium paste may contain silicon, with a silicon content ranging from 0 to 20 wt%. A TiAl alloy is formed at the interface between the semiconductor layer and the N-type and P-type electrodes, to block the diffusion of oxygen from the semiconductor layer into the Al metal electrodes.This is different from other materials commonly used in photovoltaic cells, such as TiN, TiON, or Ti, which present the following performance issues when applied to solar cells although they can also block the diffusion of Al or Cu metals:1. As shown in Fig. 9, due to their high electrical conductivity, they cannot be used in back-contact solar cells. Electrons collected from the N-type doped region can flow through these materials and recombine with holes from the P-type doped region, resulting in significant current leakage.2. As shown in Fig. 10, due to their high light reflectivity, the bifaciality is very low. Since most light is either absorbed or reflected, the efficiency of solar cell would be very low when illuminating the back surface.Therefore, in the present invention, TiO₂, WO₃, MoO₃, TeO₂ or NiO is used as the material for the semiconductor layer to block Al diffusion. Due to low electrical conductivity and low light reflectivity / absorptivity, these materials are particularly suitable for bifacial light-receiving solar cells.Embodiment 2This embodiment differs from Embodiment 1 in that, as shown in Fig. 1(b), SiOₓ is deposited on the semiconductor layer 5 to serve as a passivation layer 6, and the metal electrodes contacts with the semiconductor layer 5 by extending through the passivation layer 6. The materials of the passivation layer may be a single layer or a combination of multiple layers of SiNₓ, SiOₓ, SiONₓ or Al₂O₃. The passivation layer can form a stable surface layer to reduce electron recombination and surface reflection, thereby enhancing the efficiency of the solar cell.Embodiment 3This embodiment differs from Embodiment 2 in that, as shown in Fig. 1(c), the positions of the semiconductor layer 5 and the passivation layer 6 are inverted. After depositing the passivation layer 6 over the doped polysilicon and intrinsic polysilicon, localized portions of the passivation layer 6 above the P-type doped region 3 and the N-type doped region 4 are removed via laser processing to form contact holes. Subsequently, the semiconductor layer 5 is deposited entirely over the passivation layer 6, allowing the semiconductor layer 5 to contact with the P-type doped region 3 and the N-type doped region 4 through the contact holes.Embodiment 4This embodiment differs from Embodiment 1 in that, in the step S4, as shown in Fig. 6, the semiconductor layer 5 over the P-type doped region 3 is thinner than the semiconductor layer 5 over the N-type doped region 4. In this embodiment, as shown in Fig. 7, laser ablation is employed to make the semiconductor layer at the top of the polysilicon in the P-type doped region slightly thinner. The thickness of semiconductor layer above the P-type doped region is 40 nm, while the thickness of semiconductor layer above the N-type region is 60 nm. The laser in this embodiment is ultraviolet light with a wavelength of 355 nm and an energy density of 0.1 to 0.5 J / cm². The ultraviolet laser is particularly suitable due to its good selective absorptivity of the second semiconductor which possesses a wider band gap.In addition, the semiconductor layer over the P-type doped region can be made thinner than that over the N-type doped region by forming a metal alloy on the semiconductor layer above the P-type doped region. As shown in Fig. 8, a thin TiO₂ semiconductor layer is first formed on the polysilicon layer, then Ti metal is simultaneously formed at the top of the semiconductor layer. A first type of aluminium paste is printed and sintered only over the P-type doped region, such that a TiAl alloy and a P-type electrode are formed on the P-type doped region, while TiO₂ is formed in other areas. A second type of aluminium paste is printed and sintered over the N-type doped region, so that the semiconductor layer above the P-type doped region is thinner than that above the N-type doped region.By controlling the semiconductor thicknesses over the P-type and N-type doped regions to be different, it is possible to optimize the aluminium contact resistance in the P-type doped region 3 while simultaneously preventing damage caused by aluminium diffusion in the N-type doped region 4. Specific research will be discussed below. Research indicates that the diffusion of aluminum into the tunneling oxide layer / doped polysilicon causes passivation damage to the tunneling oxide layer / doped polysilicon:1. Doping problem of aluminium into the N-type doped polysilicon region: Aluminium in diffusion causes doping of Al in the polysilicon layer of the N-type doped region, and the increased Al doping eventually converts the N-type doping into P-type doping, thereby reducing the N-type doped efficiency of the polysilicon. In contrast, P-type doped polysilicon has no such issue due to same polarity with Al doping.2. Further diffusion problem of aluminium into the tunneling oxide layer: This results in passivation loss for both P-type and N-type doped polysilicon.Consequently, an investigation was conducted into the optimal thickness of the semiconductor layer corresponding to N-type doping and P-type doping.Fig. 11a) shows the contact resistance characteristics when in contact with the aluminium electrode in the N-type doped polysilicon and the semiconductor layer, while Fig. 11b) shows the contact resistance characteristics when in contact with the aluminium electrode in the P-type doped polysilicon and the semiconductor layer.As shown in Fig. 11a), in the dual-layer structure of N-type doped polysilicon and the semiconductor layer, aluminium exhibits excellent contact resistance; and the contact resistance remains highly stable with minimal fluctuation despite changes in the semiconductor layer's thickness. This is because the tunneling oxide layer applied to the semiconductor layer has good energy-level alignment with the conduction band of polysilicon of the N-type doped region.As shown in Fig. 11b), in the dual-layer structure of P-type doped polysilicon and the semiconductor layer, the contact resistance decreases as the thickness is reduced, and the resistance decreases as the thickness is reduced. This is attributed to the energy-level misalignment of valence band between the polysilicon of the P-type doped region and the semiconductor layer. Under a certain thickness, the tunneling effect becomes the dominant effect for electron passing through the energy bands of semiconductor layer, thereby reducing the contact resistance. As previously mentioned, the difficulty in applying aluminium pastes and high-temperature sintering processes to the doped polysilicon arises because: 1) aluminium reacts with silicon to form p-type doping; and 2) aluminium diffuses into the tunneling oxide layer beneath the doped polysilicon, thereby destroying the passivation characteristic of the oxide film.It is evident that, provided there is no passivation loss of the doped polysilicon, a thinner semiconductor layer results in lower contact resistance. Furthermore, when materials such as TiO₂ are used as the semiconductor layer, its energy band arrangement matches well with that of polysilicon of the N-type doped region, facilitating efficient electron collection (as its resistivity is not strongly dependent on the thickness of the semiconductor layer). For P-type doped polysilicon, holes can be collected via TiO₂. Consequently, TiO₂ over the P-type doped region is thinner, thereby obtaining lower resistivity.Fig. 12 presents measurement results showing the degradation of passivation effect caused by aluminium diffusion in the dual-layer structure of doped polysilicon and the semiconductor layer. Photoluminescence (PL) detection—an analytical technique widely used in the solar cell industry to analyze changes in passivation characteristic—was employed here to analyze the degradation of passivation effect caused by aluminium diffusion; the results shown represent the average PL intensity.As shown in Fig. 12, a decrease in PL intensity indicates a reduction in passivation characteristic caused by aluminium diffusion. Especially, in the N-type doped polysilicon region, PL intensity decreases dramatically even if the semiconductor layer is relatively thick. This occurs because the diffusion and doping of aluminium into the N-type polysilicon diminish the field passivation effect of the N-type doping. Fig. 10 reveals that, once the semiconductor layer thickness is reduced to a certain range, the PL intensity for both P-type and N-type doped polysilicon reaches a turning point and then remains unchanged.Accordingly, the present invention proposes an optimal thickness range for the semiconductor layer: 40 to 70 nm for the semiconductor layer over the N-type doped region, and 20 to 70 nm for the semiconductor layer over the P-type doped region. In other words, within the optimal thickness range for the semiconductor layer, the polysilicon of the N-type doped region will not be doped by Al diffusion; consequently, its passivation quality will not be degraded due to P-type doping, resulting in high PL intensity, excellent passivation characteristic, and lower contact resistance with the Al metal electrode. Meanwhile, in the thinner P-type doped region, although Al diffuses into the polysilicon, it does not diffuse into the tunneling oxide layer; furthermore, Al doping in the P-type doped region does not compromise the passivation quality while simultaneously achieving lower contact resistance with the Al metal electrode. Thus, the solar cell of the present invention enables the use of low-cost pastes to form metal electrodes while exhibiting high performance.The technical schemes provided by the present invention have been described in detail above, and specific examples have been used to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are intended solely to facilitate the understanding of the method and core concepts of the present invention. Furthermore, those skilled in the art may make modifications to the specific implementations and application scopes based on the concepts of the present invention. Therefore, the content of this specification should not be construed as limiting the present invention. 

Claims

1. A low-cost and high-performance solar cell, comprising a silicon wafer, and a tunneling oxide layer (1) and doped polysilicon formed on the silicon wafer, wherein an N-type doped region (4) and a P-type doped region (3) are formed on the doped polysilicon, with intrinsic polysilicon (2) spacing apart the N-type doped region (4) and the P-type doped region (3); a semiconductor layer (5) is formed on the doped polysilicon and the intrinsic polysilicon (2), and the materials of the semiconductor layer (5) comprises a single layer or a combination of multiple layers of TiO2, WO3, MoO3, TeO2, or NiO; an N-type electrode (8) is formed on the semiconductor layer (5) corresponding to the N-type doped region (4), and a P-type electrode (7) is formed on the semiconductor layer (5) corresponding to the P-type doped region (3), with the N-type electrode (8) and the P-type electrode (7) being in contact with the semiconductor layer (5).

2. The low-cost and high-performance solar cell according to claim 1, wherein the thickness of the doped polysilicon is 20 nm to 100 nm, and the thickness of the semiconductor layer (5) is 10 nm to 100 nm.

3. The low-cost and high-performance solar cell according to claim 1, wherein the semiconductor layer (5) above the P-type doped region (3) has the same thickness as, or a smaller thickness than, the semiconductor layer (5) above the N-type doped region (4).

4. The low-cost and high-performance solar cell according to claim 1, wherein the thickness of the semiconductor layer (5) above the N-type doped region (4) is 40 to 70 nm, and the thickness of the semiconductor layer (5) above the P-type doped region (3) is 20 to 70 nm.

5. The low-cost and high-performance solar cell according to claim 1, wherein a metal alloy is formed at the interface between the semiconductor layer (5) and the P-type electrode (7) and / or the N-type electrode (8).

6. The low-cost and high-performance solar cell according to claim 1, wherein the semiconductor layer (5) contains 0 to 5 wt% of dopant, and the dopant comprises one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N) and oxygen (O).

7. The low-cost and high-performance solar cell according to claim 1, wherein the P-type electrode (7) and / or the N-type electrode (8) contains Al, Ag, Cu, or a mixture thereof.

8. The low-cost and high-performance solar cell according to claim 1, wherein the P-type electrode (7) and / or the N-type electrode (8) are formed from an aluminium paste, and the silicon content in the aluminium paste is 0 to 20 wt%.

9. The low-cost and high-performance solar cell according to claim 1, further comprising a passivation layer (6), wherein the passivation layer (6) is formed on the semiconductor layer (5).

10. The low-cost and high-performance solar cell according to claim 1, further comprising a passivation layer (6), wherein the passivation layer (6) is formed on the doped polysilicon and the intrinsic polysilicon (2); the semiconductor layer (5) is formed on the passivation layer (6); the semiconductor layer (5) extends through the passivation layer (6) to be in contact with the doped polysilicon; and the materials of the passivation layer (6) is a single layer or a combination of multiple layers of SiNx, SiOx, SiONx or Al2O3.

11. A manufacturing process for the low-cost and high-performance solar cell according to any one of claims 1 to 10, comprising the following steps:S1: forming a tunneling oxide layer (1) and intrinsic polysilicon (2) on a silicon wafer;S2: selectively implanting boron and phosphorus into the intrinsic polysilicon (2) to form doped polysilicon, wherein N-type doped regions (4) and P-type doped regions (3) are alternately formed on the doped polysilicon, and intrinsic polysilicon (2) is reserved between the N-type doped regions (4) and the P-type doped regions (3) to serve as isolation;S3: forming a semiconductor layer (5) on the doped polysilicon; andS4: forming an N-type electrode (8) and a P-type electrode (7) on the semiconductor layer (5), so that the N-type electrode (8) is in contact with the semiconductor layer (5) above the N-type doped regions (4) and the P-type electrode (7) is in contact with the semiconductor layer (5) above the P-type doped regions (3).

12. The manufacturing process for a low-cost and high-performance solar cell according to claim 11, wherein, in the step S2, boron and phosphorus are selectively implanted via ion implantation, printing and thermal treatment of doped paste, or the use of a mask and a doping diffusion furnace;in the step S3, the semiconductor layer (5) over the P-type doped region (3) is subjected to laser ablation treatment, or a metal alloy is formed on the semiconductor layer (5) over the P-type doped region (3), so that the thickness of the semiconductor layer (5) over the P-type doped region (3) is less than that of the semiconductor layer (5) over the N-type doped region (4); andin the step S4, the N-type electrode (8) and the P-type electrode (7) are simultaneously formed by printing and sintering a metal paste on the semiconductor layer (5), or the N-type electrode (8) and the P-type electrode (7) are separately formed by printing and sintering a metal paste on the semiconductor layer (5). 

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