Substrate with vias and associated manufacturing processes

Abstract

The invention relates to a substrate (3) comprising a semiconductor-based first layer (30), and a second layer (31) located above the first layer. The substrate (3) contains a plurality of buried vias (32) extending from the second layer (31) over a segment of the first layer (30), each via (32) being bounded by a sidewall (320), a bottom wall (321), and a top wall (322) that is opposite the bottom wall (321), and at least one set (32a) of the plurality of vias (32) forms a pattern (32b) that repeats in at least one direction of the plane of main extension of the first and second layers (30, 31). The substrate (3) thus forms a generic substrate allowing use of vias to fabricate a microelectronic device to be facilitated.

Description

[0001] “Substrate comprising vias and associated manufacturing processes”

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the field of substrates intended for manufacturing electronic devices and more particularly microelectronic devices. These substrates can ultimately allow electrical and mechanical connection of electrical elements of components. The invention finds advantageous, but not limited, application in the manufacture of microelectronic devices.

[0004] STATE OF THE ART

[0005] There is an interest in manufacturing microelectronic devices using vias extending perpendicular to the main extension plane of the substrate. This may be particularly interesting for the manufacturing of microelectromechanical systems (MEMS). It may also be particularly interesting for the manufacturing of component assemblies on substrates comprising vias to form through-hole contacts in order to be able to interconnect these components on the front and back faces of a substrate, to obtain a microelectronic device. The components can thus be connected to a printed circuit, for example, via a package. These substrates may in particular be semiconductor substrates, for example of the semiconductor-on-insulator type, and in particular silicon-on-insulator (SOI).

[0006] The etching and filling of these vias (commonly referred to as TSV, short for Through-Silicon-Via for silicon-based substrates) with an electrically conductive or semiconducting material are fairly specific process steps and are often carried out by assemblers (commonly referred to as OSAT, short for Outsourced Semi-conductor Assembly and Test) and not by foundries.

[0007] There are two types of vias depending on their manufacturing time in the microelectronic device manufacturing chain. So-called "TSV-middle" vias are generally manufactured in the middle of the process, after the fabrication of a component's patterns during the Front-end-of-line (abbreviated FEOL, which can be translated as the beginning of the manufacturing line) but before the deposition of the metal layers of the Back-end-of-line (abbreviated BEOL, which can be translated as the end of the manufacturing line). This generally requires a transfer of the substrate and components from the foundry to the assembler for the fabrication of the vias, then a return to the foundry for the BEOL steps, and finally another transfer to the assembler to finalize the process. These manufacturing steps are very constrained in terms of flatness and contamination, which is not very compatible with these back-and-forths between the foundry and the assembler.

[0008] TSV-last vias can be manufactured at the end of the process, after the FEOL and BEOL steps. This generally requires a single transfer from the foundry to the assembler, after the BEOL steps. However, the via geometries that can be achieved are limited. In particular, the via density that can be achieved is limited.

[0009] There is therefore a need to obtain these structures without depending on other manufacturing steps in the chain.

[0010] An object of the present invention is therefore to facilitate the fabrication of vias in a microelectronic device.

[0011] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated.

[0012] SUMMARY OF THE INVENTION

[0013] To achieve this objective, according to a first aspect, a substrate is provided, in particular for a microelectronic device, comprising: - a first layer based on, and preferably made of, a semiconductor material,

[0014] - a second layer on top of the first layer.

[0015] The substrate includes a plurality of buried vias extending from the second layer over a portion of the first layer, each via being delimited by a side wall, a bottom wall, and a top wall opposite the bottom wall, and at least one set of the plurality of vias forms a repeating pattern along at least one direction of the main extension plane of the first and second layers.

[0016] Thus, the substrate is generic and comprises non-opening vias pre-filled or configured for filling by a subsequent electrically conductive or semiconductive member. This makes it possible to provide the vias independently of the other steps in the production of a microelectronic device. The substrate comprising the buried vias can be used to carry out the deposition of layers, for example FEOL and BEOL, and then the vias can be used to produce the desired electrically conductive or semiconductive member, for example electrical interconnects. Furthermore, since the vias are pre-fabricated, the geometries of the vias are not limited.

[0017] The substrate comprises a matrix of vias that can be selected in whole or in part in order to produce the desired electrically conductive or semiconductive members as best suited to the desired geometry. The generic substrate comprising these vias therefore makes it easier to manufacture the vias and the conductive or semiconductive member, in particular by being able to adapt to different microelectronic devices.

[0018] It is therefore understood that the manufacture of vias is facilitated, particularly with regard to the other stages of manufacturing a microelectronic device, by making it possible to adapt to different microelectronic devices with the same generic substrate. The manufacture of vias filled by the electrically conductive or semiconducting member is particularly facilitated.

[0019] A second aspect relates to a method of manufacturing the substrate, comprising:

[0020] - a supply of a support sub-substrate comprising at least a first layer based on a semiconductor material, the support sub-substrate having an exposed surface,

[0021] - forming a plurality of vias such that the vias extend from the exposed surface over a portion of the first layer, each via being delimited by a side wall and a bottom wall, at least one set of vias forming a pattern repeating along at least one direction of the main extension plane of the first and second layers,

[0022] - a supply of a donor sub-substrate comprising a surface layer having an exposed surface,

[0023] - an assembly of the support sub-substrate and the donor sub-substrate by their exposed surfaces, so as to cover the vias, each via then being delimited by the side wall, the bottom wall, and an upper wall opposite the bottom wall.

[0024] This process thus allows the fabrication of the matrix of buried vias on the substrate. This process has the effects and advantages described in relation to the first aspect.

[0025] A third aspect relates to a method of manufacturing a microelectronic device comprising:

[0026] - a provision of a substrate according to the first aspect and / or a substrate manufactured by the method according to the second aspect, having a front exposed surface and a rear exposed surface,

[0027] - forming at least one portion of the device layer by depositing said portion on at least one of the front or rear exposed surfaces of the substrate, for example a first exposed surface, and for example the front exposed surface, and / or etching at least one of the front or rear exposed surfaces of the substrate, for example the first exposed surface, and for example the front exposed surface, configured to form said portion,

[0028] - at at least one via, etching by one of the front or rear exposed surfaces of the substrate, for example a second exposed surface distinct from the first, and for example the rear exposed surface, until reaching the via, and: o continuing the etching to reach the at least one layer portion of the device, or o at the at least one via, etching by the other of the front or rear exposed surfaces of the substrate, for example by the first exposed surface, and for example the front exposed surface, until reaching the via,

[0029] - the deposition of at least one electrically conductive or semiconductive member so as to provide electrical continuity at least to the via and the portion of the device layer, for example in addition to the front and / or rear surface of the substrate.

[0030] Thus, the provided substrate allows the formation of a microelectronic device, then the opening of buried vias to produce the desired electrically conductive or semiconducting organ. This can be achieved in an easier way compared to existing solutions.

[0031] BRIEF DESCRIPTION OF THE FIGURES

[0032] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0033] Figures 1A and 1B respectively represent cross-sectional and cross-sectional views in the main extension plane of the first and second layers of the substrate according to an exemplary embodiment.

[0034] Figures 2A-2C show cross-sectional views of different via configurations.

[0035] Figures 3A and 3B respectively represent cross-sectional and cross-sectional views in the main extension plane of the first and second layers, of the substrate according to another exemplary embodiment.

[0036] Figures 4A to 4E represent cross-sectional views of the steps of the method of manufacturing the substrate according to an exemplary embodiment.

[0037] Figures 5A to 5D represent cross-sectional views of the steps of the method of manufacturing the substrate according to another exemplary embodiment.

[0038] Figures 6A to 6D represent cross-sectional views of the steps of the method of manufacturing the microelectronic device according to an exemplary embodiment.

[0039] Figures 7 and 8A to 8D represent cross-sectional views of the steps of the method of manufacturing the microelectronic device according to two other exemplary embodiments.

[0040] Figures 9A to 9C represent cross-sectional views of the steps of the method of manufacturing the microelectronic device according to an example in which a via comprises several portions each having a different configuration.

[0041] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, the relative dimensions of the sub-substrates and substrate, the layers, the vias and the walls are not representative of reality.

[0042] DETAILED DESCRIPTION OF THE INVENTION Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set forth below.

[0043] According to one example, for at least some of the vias, and for example for each via, the vias are at least partly filled with material(s).

[0044] In one example, each via has at least one transverse dimension between 1 pm and 30 pm. In one example, all transverse dimensions of each via are between 1 pm and 30 pm.

[0045] According to one example, at least a portion of the vias, and preferably each via, has an aspect ratio greater than or equal to 10, with the longest dimensions oriented along a thickness dimension of the first and second layers. This form factor is particularly suitable for obtaining a high density of vias on the substrate, and in particular in synergy with the ranges of pitch values ​​set out below.

[0046] According to one example, within a set of vias, two patterns of vias, for example two vias, repeating successively are separated by a constant pitch along at least one direction of the main extension plane of the first and second layers.

[0047] According to one example, the pitch is substantially between 50 pm and 300 pm, preferably between 100 pm and 200 pm. This pitch allows for a better density of vias in the substrate. Thus, a greater interconnection density is possible. In addition, the adaptability of the substrate to different microelectronic devices is improved.

[0048] In one example, the substrate includes multiple sets of vias each forming a repeating pattern along at least one direction of the main extension plane of the first and second layers. The generic substrate may thus include different arrangements of via patterns to accommodate various microelectronic devices.

[0049] According to one example, at least one via, and preferably at least a portion of the plurality of vias, and preferably each via, has at least one via configuration in which:

[0050] - the sidewall of the via is made of a dielectric material, and the via is filled with an electrically conductive or semiconducting material or the via is hollow,

[0051] - the side wall of the via is made of a dielectric material, and the via is filled with the material of the first layer,

[0052] - the side wall of the via is made of the material of the first layer and the via is hollow. The vias can therefore be solid or hollow, and possibly already electrically isolated from the first layer. When the side wall of the via is made of a dielectric material, the vias formed in the substrate have a dielectric layer at least on their side wall, prior to the use of the substrate in a process for manufacturing a microelectronic device. The wall of dielectric material being formed beforehand, it allows good insulation of the vias once filled with the conductive or semiconductive material, while being compatible with the steps of FEOL or temporary mounting of a support.

[0053] According to one example, at least one via, and preferably at least a portion of the plurality of vias, and preferably each via of at least one set, has a first via configuration on a first portion, and a second via configuration distinct from the first via configuration on a second portion, the first and second portions extending successively along a thickness dimension of the first and second layers. According to one example, a portion of these vias may be hollow, and another portion may be solid. This type of via makes it possible to make narrower via widths for the solid portion, and therefore more vias with a given surface area. Their accessibility is made easier by the hollow portion already formed.

[0054] According to one example, the substrate comprising several sets of vias each forming a pattern repeating along at least one direction of the main extension plane of the first and second layers, at least one set, and preferably each set, has at least one via configuration distinct from another set. The generic substrate can thus comprise different via structures to adapt to various microelectronic devices.

[0055] According to one example, the substrate further comprises a marker configured to allow the alignment of the substrate. This further facilitates the manufacturing of the microelectronic device, by facilitating the alignment of the substrate, and in particular for carrying out the photolithography steps necessary for the construction of the FEOL and the BEOL, and therefore the opening of the vias.

[0056] In one example, the vias are parallel to each other.

[0057] According to one example, the vias have a longitudinal dimension oriented along a thickness dimension of the first and second layers.

[0058] In one example, the vias extend in a direction parallel to the normal to the main extension plane of the first and second layers.

[0059] According to one example, at least a portion of the vias, and preferably each via of the at least one set, have a cross-section, for example in a plane substantially parallel to the main extension plane of the first and second layers, of square, polygonal or cylindrical shape.

[0060] In one example, the second layer is placed on top of the first layer by being in direct contact with it.

[0061] According to one example, at least a portion of the vias, and preferably each via, has a cross-section, for example in a plane substantially parallel to the main extension plane of the first and second layers, the ratio of the largest dimension to the smallest dimension of which is less than or equal to 3, preferably less than or equal to 2. The vias are therefore quite distinct from other structures such as trenches.

[0062] According to one example, at least a portion of the vias, and preferably each via of the at least one set, has a symmetry of revolution about an axis substantially parallel to a thickness dimension of the first and second layers. Preferably, at least a portion of the vias, and preferably each via of at least one set, is cylindrical. Thus, the bottom wall of the vias is more homogeneous than for non-cylindrical shapes, for example a square shape for which the corners will be shallower than the center, following the etching of the vias. A cylindrical shape minimizes this effect. In addition, the mechanical stresses are lower for cylindrical vias which do not have the singularities of the corners. This is advantageous for heat treatments during the fabrication of the circuits.

[0063] According to one example, at least one via, and preferably each via of at least one set, over at least a portion of a longitudinal dimension of said via, is fully surrounded by a groove extending from the second layer over a portion of the first layer. The groove makes it possible to improve the electrical insulation between the vias. The groove is thus manufactured beforehand and independently of the other manufacturing steps of the microelectronic device. The groove is thus compatible with the FEOL steps taking place at high temperature. In addition, since the groove is manufactured beforehand, its geometry is not limited by the other manufacturing steps of the microelectronic device.

[0064] In one example, each groove is not filled with a solid material. Each groove is preferably filled with an electrically insulating gaseous atmosphere, for example air.

[0065] According to one example, each groove is delimited by a bottom wall, a side wall and a top wall opposite the bottom wall. For at least one groove, and preferably for each groove, at least a portion of the side wall and the bottom wall may be made of the same material as that of the first layer. The insulation of the vias is indeed sufficient thanks to the insulating atmosphere contained in the groove. Alternatively, for at least one groove, and preferably for each groove, at least a portion of the side wall and the bottom wall may be made of a dielectric material, for example the same dielectric material as the walls of the via. Thus, the electrical insulation of the via is further improved.

[0066] In one example, the groove is concentric with the via. This makes it possible, in particular, to reduce the parasitic capacitance between the via and the substrate and to increase the breakdown voltage.

[0067] According to one example, the groove extends from the second layer into the first layer over a longitudinal dimension less than a longitudinal dimension of the via, preferably the longitudinal dimension of the groove is less than or equal to the longitudinal dimension of the via, preferably plus or minus 5 μm. Thus, the groove surrounds the via over at least a portion and preferably substantially the entire longitudinal dimension.

[0068] According to one example, the semiconductor material is chosen from the group consisting of silicon Si, germanium Ge, SiGe, a III-V material (for example GaN, InN, InGaAs, GaP, InP, InAs, AsGa...), an III-VI material, materials with a wide band gap, for example greater than 3 eV.

[0069] In one example, the semiconductor material comprises, and preferably is, silicon.

[0070] According to one example, the piezoelectric material is selected from lithium tantalate (LiTaOs), lithium niobate (LiNbOs), potassium sodium niobate (K x Nai. x NbO3 or KNN), barium titanate (BaTiOs), quartz, lead zirconate titanate (PZT), a compound of lead-magnesium niobate and lead titanate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AIN) or aluminum scandium nitride (AIScN).

[0071] According to one example, the dielectric material is a semiconductor oxide, and preferably silica of chemical formula SiO2.

[0072] According to an example of the method of manufacturing the substrate, the formation of the plurality of vias is configured such that at least a portion of the plurality of vias has at least one of the following via configurations:

[0073] - the sidewall of the via is made of a dielectric material, and the via is filled with an electrically conductive or semiconducting material or the via is hollow,

[0074] - the sidewall of the via is made of a dielectric material, and the via is filled with the material of the first layer, the sidewall of the via is made of the material of the first layer and the via is hollow.

[0075] According to one example, the via configurations differ for at least one of the following properties: the dielectric or non-dielectric nature of the sidewall of the via; the shape of the via (and in particular the cross-section), the dimension, the filling material of the via, the hollow or solid character of the via.

[0076] According to one example, the formation of the plurality of vias comprises, for at least one set of vias and on at least a first portion of said vias, an etching of at least one periphery of the via.

[0077] In one example, the etching is configured to etch only the periphery of the via. Equivalently, the etching is configured to etch a groove forming the periphery of the via. Thus, after an oxide forms in the groove, the sidewall of the via is made of a dielectric material, and the via is filled with the material of the first layer.

[0078] In another example, the etching is configured to etch the via over substantially its entire volume. Thus, the sidewall of the via may be made of the material of the first layer and the via may be hollow. Alternatively, after formation of an oxide around the periphery of the formed cavity, the sidewall of the via may be made of a dielectric material and the via may be hollow or filled.

[0079] According to one example, the formation of the plurality of vias comprises, following the etching of at least the periphery of the via, a formation of a dielectric material on at least the etched periphery of the via so as to form the sidewall of the via in dielectric material.

[0080] According to one example, when etching at least the periphery of the via, the via is etched over substantially its entire volume, and the formation of the plurality of vias comprises, following the formation of a dielectric material on at least the etched periphery of the via so as to form the sidewall of the via made of dielectric material, a deposition of an electrically conductive or semiconductive material so as to at least partially fill the via. Thus, the sidewall of the via is made of the dielectric material, and the via is filled with the electrically conductive or semiconductive material.

[0081] We therefore understand that these different steps make it possible to achieve the via configurations previously described.

[0082] In one example, forming the plurality of vias includes forming multiple sets of vias each forming a repeating pattern along at least one direction of the main extension plane of the first and second layers. In one example, forming the sets of vias is configured such that each set has at least one via configuration distinct from another set.

[0083] In one example, the formation of the plurality of vias is configured such that at least one via, and preferably at least a portion of the plurality of vias, has a first via configuration over a first portion, and a second via configuration distinct from the first via configuration over a second portion, the first and second portions extending along a thickness dimension of the first and second layers.

[0084] In one example, forming a dielectric material at at least the bottom wall and the side wall of the plurality of vias comprises:

[0085] - thermal oxidation so as to oxidize the semiconductor material of the first layer at least at the bottom wall and the side wall, and / or

[0086] - a deposit of the dielectric material at least on the bottom wall and the side wall.

[0087] These techniques, and particularly thermal oxidation, allow good conformity of the walls made of dielectric material to be obtained. Since thermal oxidation is conformal, it allows for an oxide to be obtained that is both dense and of uniform thickness on the bottom and side walls. Thermal oxidation is therefore particularly advantageous in synergy with high via form factors. Compared to deposition, thermal oxidation also allows smoothing of the etched via wall and limits the presence of defects between the semiconductor material of the first layer and the dielectric.

[0088] According to one example, when the sidewall is made of dielectric material, the sidewall of the plurality of vias has a transverse dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0089] According to one example, when the bottom wall is made of dielectric material, the wall has a longitudinal dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0090] According to one example, the surface layer of the donor sub-substrate is a layer based on, and preferably made of, a material selected from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material.

[0091] According to an example:

[0092] - the support sub-substrate further comprises a surface layer based on, and preferably made of, a dielectric material, for example an oxide, overlying the first layer, the surface layer having the exposed surface, and / or

[0093] - the surface layer of the donor sub-substrate is a layer based on, and preferably made of, a dielectric material, for example an oxide, overlying a layer based on a material chosen from a semiconductor material or a piezoelectric material.

[0094] It is therefore understood that the buried oxide layer of the substrate can come from the donor sub-substrate and / or the support sub-substrate.

[0095] According to one example, the surface layer of the donor substrate is based on, preferably made of, one of a semiconductor material or a dielectric material. Depending on whether the surface layer is based on a semiconductor material or a dielectric material, it is understood that the upper wall of the vias, and where appropriate of the grooves, is based on or made of a semiconductor material or a dielectric material.

[0096] According to one example, the method for manufacturing the substrate further comprises, prior to assembling the support sub-substrate and the donor sub-substrate, etching a groove completely surrounding at least one via over at least a portion of a longitudinal dimension of said via, the groove extending from the surface layer into the first layer. The effects and advantages described in relation to the groove are therefore obtained.

[0097] In one example, the method includes forming an embrittlement zone at a depth of the surface of the top layer of the donor substrate, and then separating the donor substrate at the embrittlement zone.

[0098] According to one example, the method for manufacturing the microelectronic device comprises selecting at least one via to be etched from the plurality of vias, only a portion of the plurality of vias being selected as the via to be etched. Thus, it is possible to select the vias to be etched from the vias present in the substrate. The method is thus adaptable according to the desired microelectronic device configuration, for different microelectronic devices. This selection can be made prior to etching by one of the front or rear exposed surfaces of the substrate.

[0099] According to one example, the selection of the at least one via to be etched comprises the application, on said exposed front or rear surface of the substrate, of a mask comprising openings located directly above the at least one via to be etched, followed by etching so as to reach the at least one via to be etched. Thus, a potential weakening of the wall of the vias to be etched is avoided, compared to an extensive thinning of the face of the substrate. This etching thus etches the layer at right angles to the at least one via to be etched until it opens into the at least one via to be etched.

[0100] According to one example, when the method implements etching through the other of the front or rear exposed surfaces of the substrate, until reaching the via, the selection of the at least one via to be etched from the plurality of vias comprises the application, on said other front or rear exposed surface of the substrate, of a mask comprising openings located directly above the at least one via to be etched, and the method further comprises etching so as to reach the at least one via to be etched. This is particularly advantageous when the via is filled with an electrically conductive or semiconductive material, including the material of the first layer. This makes it possible to reach the via through the rear and front faces of the substrate, to provide electrical continuity to the via.

[0101] According to one example, the deposition of the electrically conductive or semiconductive member is configured so as to further cover with an electrically conductive or semiconductive layer at least a portion of the exposed front and / or rear surface of the substrate.

[0102] In one example, the method includes patterning the back electrically conductive or semiconductive layer.

[0103] In one example, the method includes passivating the rear exposed surface of the substrate.

[0104] According to one example, the method of manufacturing a microelectronic device comprises:

[0105] - between the formation of the at least one layer portion of the device, and the etching by the rear exposed surface of the substrate, the mounting of a support on the front exposed surface of the substrate, and

[0106] - after depositing the electrically conductive or semi-conductive organ so as to fill the electrical cavity, dismantling the support.

[0107] The support thus makes it easier to handle the substrate.

[0108] A microelectronic device is any type of device made using microelectronics. These devices include, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices, as well as optical or optoelectronic devices. It may be a device intended to perform an electronic, optical, mechanical, etc. function. It may also be an intermediate product intended solely for the production of another microelectronic device. It may also be a structure of passive electrical interconnections.

[0109] It is specified that, in the context of the present invention, the term "on" or "above" does not necessarily mean "in contact with". Thus, for example, the deposition of a layer on another layer does not necessarily mean that the two layers are directly in contact with each other but it does mean that one of the layers at least partially covers the other by being either directly in contact with it, or by being separated from it by a film, yet another layer or another element.

[0110] A layer can also be composed of several sub-layers of the same material or of different materials.

[0111] An element “based” on a material A means an element comprising this material A only or this material A and possibly other materials.

[0112] In the following detailed description, terms such as "longitudinal" and "transverse" may be used. These terms must be interpreted relative to the substrate or the thickness dimension of the devices. Thus, a longitudinal dimension, a height, a depth or a thickness of an element or a layer means a dimension according to the thickness of the substrate which carries or contains it. A width, or a section or a transverse dimension means a dimension perpendicular to the thickness of the substrate.

[0113] Certain parts of the substrate or device of the invention may have an electrical function. Some are used for electrical conduction properties and electrically conductive or equivalent means elements formed from at least one material having sufficient conductivity, in the application, to achieve the desired function. Other parts, on the contrary, are used for electrical insulation properties and all materials having sufficient resistivity to achieve this insulation are concerned and are in particular called dielectric or electrically insulating.

[0114] The word "dielectric" more particularly describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 4.

[0115] "Direct bonding" means bonding without the addition of adhesive material (such as glue or polymer in particular) which consists of bringing relatively smooth surfaces into contact (with a root mean square roughness RMS, typically less than 5 Â, 10' 10 m), for example carried out at room temperature and in an ambient atmosphere, in order to create adhesion between them.

[0116] According to one embodiment, the direct bonding of two substrates means that the bonding is obtained by the chemical bonds which are established between the two surfaces brought into contact. These chemical bonds can be, for example, Van der Waals bonds and / or strong, covalent chemical bonds, in particular when the bonding is assisted by plasma activation or followed by a strengthening heat treatment (typically 200 to 1200°C for 1 hour).

[0117] Direct bonding can be achieved without applying significant pressure to the structure to be joined. Light pressure may simply be applied to initiate the bonding. Thermal annealing may also be performed to strengthen the bond.

[0118] A parameter "substantially equal / greater / less than" a given value means that this parameter is equal / greater / less than the given value, to within plus or minus 10%, or even plus or minus 5%, of this value.

[0119] The substrate 3 is now described according to several exemplary embodiments with reference to FIGS. 1A to 2C.

[0120] As for example illustrated by Figure 1A, the substrate 3 comprises a first layer 30, based on or made of a semiconductor material. According to one example, the semiconductor material comprises, and preferably is, silicon. Note that as described later, other semiconductor materials are conceivable. The first layer 30 has a thickness L30, for example substantially between 100 pm and 800 pm.

[0121] The substrate 3 further comprises a second layer 31. As illustrated by FIGS. 1A and 2A, the second layer 31 may be based on or made of a dielectric material. According to one example, the dielectric material comprises, and preferably is, a semiconductor oxide, for example silica of formula SiC>2. The second layer 31 surmounts the first layer 30, preferably by being in direct contact with it. As illustrated by FIG. 2B, the second layer 31 may alternatively be based on or made of a semiconductor material, preferably monocrystalline, or of a piezoelectric material. The second layer 31 may have a thickness L31, for example greater than or equal to 10 nm, preferably 100 nm. The thickness L31 may be less than or equal to 3000 nm. The second layer 31 of the substrate 3 is preferably free of metal portions. The second layer 31 is preferably continuous in the main extension plane of the substrate 3.

[0122] According to one example, which can be illustrated by Figures 1A and 2A, the second layer 31 is surmounted by a third layer 33 based on or made of a semiconductor material, preferably monocrystalline, or a piezoelectric material. According to one example, the semiconductor material comprises, and preferably is, silicon. Note here again that as described later, other semiconductor materials are conceivable. The third layer 33 has a thickness L33, for example substantially between 10 nm and 20,000 nm. The substrate 3 can therefore comprise a structure of the semiconductor-on-insulator type, and in particular of the silicon-on-insulator (SOI) type. Note that it can be provided that the second layer 31 is not surmounted by a third semiconductor layer. The third layer 33 of the substrate 3 is preferably free of metal portions. The third layer 33 is preferably continuous in the main extension plane of the substrate 3.

[0123] According to one example, the material from which a layer 30, 31, 33 is formed is preferably continuous in the plane of extension of the layer. At least one and preferably each layer(s) 30, 31, 33 is preferably continuous over at least 80%, preferably over at least 90%, and more preferably still the entire plane of main extension of the substrate 3.

[0124] The first layer 30 and / or the second layer 31 is / are preferably monolithic^). The first layer 30 is preferably monolithic over at least the portion over which the vias 32 extend.

[0125] In the following, unless explicitly stated otherwise, it is considered, without limitation, that the substrate 3 is an SOI substrate, the first layer 30 being made of monocrystalline silicon, the second layer of SiO2 and the third layer of monocrystalline silicon.

[0126] The substrate 3 comprises vias 32 extending from the second layer 31 into the first layer 30. The vias 32 preferably extend over a longitudinal dimension L32 oriented in the direction of the thickness of the first 30 and second 31 layers. The vias 32 may be parallel to each other. The vias 32 are buried in the substrate 3, that is to say they do not open onto either of the exposed surfaces 3a, 3b of the substrate 3. The vias 32 therefore define a closed volume.

[0127] Thus, the substrate 3 comprises vias 32 for their subsequent use in a method of manufacturing a microelectronic device. This makes it possible to provide the vias independently of the other steps of producing a microelectronic device 4, as described later with reference to the method of manufacturing the microelectronic device.

[0128] The longitudinal dimension L32 may be chosen so that the vias 32 are flush with the surface of the first layer 30, at the interface with the second layer 31, as for example illustrated in FIGS. 1A to 2A and 2C. Alternatively, not illustrated here, the vias 32 may further extend over a portion of the thickness L31 of the second layer 31. This is the case for example when the donor sub-substrate 2 and the support sub-substrate 1 each have a surface layer based on a dielectric material, these surface layers together forming the second layer 31 after assembly.

[0129] The vias 32 being non-emerging, they are delimited by a side wall 320, a bottom wall 321 and an upper wall 322 opposite the bottom wall 321. Note that the front surface 3a and the rear surface 3b of the substrate 3 can be defined interchangeably with respect to the bottom walls 321 and upper walls 322 of the vias. In the following and including for the method of manufacturing the microelectronic device described later, it is considered, without limitation, that the bottom wall 321 is arranged towards the rear surface 3b of the substrate 3 and the upper wall 322 is arranged towards the front surface 3a of the substrate 3. The methods described later can however be adapted to the case where the bottom wall 321 is arranged towards the front surface 3a of the substrate 3 and the upper wall 322 is arranged towards the rear surface 3b of the substrate 3.

[0130] One and / or the other of the surfaces exposed on substrate 3 may be based on a semiconductor material, preferably monocrystalline. The vias 32 may be topped with a layer or a stack of layers comprising at least one layer based on a semiconductor material, preferably monocrystalline. It is therefore understood that the second layer 31 and / or the second layer 33 may be based on a semiconductor material, preferably monocrystalline, as described previously. Thus, the generic substrate 3 comprising the vias is compatible with the FEOL and BEOL steps.

[0131] For example, the selection of the vias to be etched 32' can be made by the front face, and for example after an etching of the substrate 3 of the vias 32 on the rear face. The selection of the vias to be etched 32' can be made by the rear face, and for example before or after an etching of the substrate 3 of the vias 32 on the front face.

[0132] According to an example that can be illustrated by Figures 1A and 1B, the vias 32 form at least one set 32a comprising a pattern 32b repeating at least once along at least one direction, preferably two directions, of the main extension plane of the first 30 and second 31 layers. These directions are preferably perpendicular. It can be provided that these directions are not perpendicular to each other. There is therefore at least one pattern 32b of vias 32 and one or more sets 32a of vias 32 repeating a pattern 32b. Each set comprises a repeated pattern 32b of via 32. The patterns 32b can be different between several sets 32a.

[0133] A pattern 32b may comprise only one via 32, or several vias 32 as illustrated in FIG. 1 B. The via pattern 32b may be of any shape. According to one example, several vias 32 may form a polygonal pattern taken in a plane parallel to the main extension plane of the first 30 and second 31 layers. The via patterns 32b may be arranged at regular intervals in the main extension plane of the first 30 and second 31 layers.

[0134] Thus, the substrate 3 may be a generic substrate comprising a matrix of vias, in which vias to be etched 32 will be chosen according to the electrically conductive or semiconductive members to be formed, as described in more detail later.

[0135] For this, the patterns 32b of vias 32 may be successively separated by a first pitch A along a first direction contained in the main extension plane of the first 30 and second 31 layers. The patterns 32b of vias 32 may be successively separated by a second pitch B along a second direction contained in the main extension plane of the first 30 and second 31 layers, distinct from the first. Preferably, these first and second directions are perpendicular. These pitches are taken center to center between a via of the pattern 32b and the corresponding via of the following pattern 32b, as illustrated in FIG. 1 B. The pitches A and / or B are preferably constant, that is to say substantially identical for each repetition of patterns.

[0136] Either or both of these pitches A and B may be substantially between 50 pm and 300 pm, preferably between 100 pm and 200 pm. These pitches may be different from each other or equal to each other, depending on the desired die geometry.

[0137] According to a preferred example, the substrate 3 comprises a single pattern 32b of via 32, preferably comprising a single via 32. According to this example, each via 32 is separated from the neighboring via(s) 32 by substantially identical pitches A and B for each pattern repetition. The pitches A and B are preferably equal to each other.

[0138] According to an example illustrated by Figures 3A and 3B, the vias 32 form several sets 32a, 32a', 32a”, i.e. at least two or more sets. Each set 32a, 32a', 32a” may comprise a via pattern 32b repeating as described above. The patterns 32b, 32b', 32b” of different sets may be different, as illustrated for example in Figure 3B.

[0139] The pattern(s) 32b may be repeated along one direction, preferably one of the two distinct directions above, of the main extension plane of the first 30 and second 31 layers, over at least 80% of the dimension of the substrate 3 along this / these direction(s). The pattern(s) 32b of vias 32 are preferably repeated, in the main extension plane of the first layer 30, over at least 80%, preferably at least 90%, and more preferably still at least 95%, of the main extension plane of the first layer 30. The pattern(s) 32b of vias 32 are further preferably repeated, in the main extension plane of the substrate 3, over at least 80%, preferably at least 90%, and more preferably still at least 95%, of the main extension plane of the substrate 3.The generic substrate 3 thus comprises one or more matrices of generic vias 32 over a large part of its surface, to facilitate the manufacture of a microelectronic device as described in detail later. These vias 32 may in particular be selected according to the desired architecture, with a generic substrate 3 which can be adapted to the manufacture of different microelectronic devices.

[0140] According to one example, at least a portion of the vias 32 and preferably each via, extends over a height greater than or equal to 50% of the thickness of the substrate 3, preferably greater than or equal to 70% of the thickness of the substrate 3.

[0141] The vias 32 may furthermore have one of several configurations, or equivalently one of several structures. For example, the vias 32 may be at least partly hollow and / or at least partly filled with a solid material. These configurations are now described with reference to FIGS. 2A to 2C, which illustrate different possible configurations of vias. The patterns 32b of repeated vias are not shown.

[0142] According to one example, the sidewall 320 of the via 32 may be made of a dielectric material, and the via 32 may be filled with an electrically conductive or semiconductive material 323. This configuration is compatible with the steps of the FEOL.

[0143] The side wall 320 of the via 32 may be made of a dielectric material and the via 32 may be hollow. Preferably, according to these examples, at least the side wall 320 and the bottom wall 321 are made of a dielectric material. The top wall 320 may be made of a dielectric material or a semiconductor material or a piezoelectric material, as will become more apparent when describing the method for manufacturing the substrate 3.

[0144] According to another example, the sidewall 320 of the via 32 may be made of a dielectric material, and the via 32 is filled with the material of the first layer 30. According to this example, the bottom wall 321 of the via may be located normal to the sidewall 320 at its end. This bottom wall may not be physically materialized by a change of material, as illustrated by the dotted lines in FIG. 2A.

[0145] According to another example, the via 32 may be hollow and not delimited by a sidewall made of dielectric material. The sidewall 320 of the via 32 may be made of the material of the first layer 30.

[0146] When via 32 is hollow, it is not filled with a solid material. Via 32 is preferably filled with a gaseous atmosphere such as air, nitrogen, or argon, possibly at a pressure less than or equal to ambient pressure.

[0147] When at least the bottom wall 321 and the side wall 320 are made of dielectric material, the via 32 once filled with an electrically conductive or semiconductive material will be electrically insulated from the first layer 30 and from the other vias 32. As a variant, the walls of the vias 32, and in particular the side wall 320, may be made of semiconductive material, and more particularly of the same material as that of the first layer 30. The electrical insulation of the vias 32 may be done subsequently during the method of manufacturing the microelectronic device from the substrate 3, described later.

[0148] The vias may have a transverse dimension D32, for example a diameter, substantially less than or equal to 30 pm, preferably substantially between 1 pm and 30 pm, preferably substantially between 5 pm and 15 pm, and even more preferably between 8 and 12 pm. Thus, the lateral dimension D32 is smaller than the typical dimensions of TSV-last, which makes it possible to have a greater number of vias 32 for the same surface area of ​​the substrate 3 in the main extension plane of the first 30 and second 31 layers, i.e. a greater density of vias 32. The longitudinal dimension of the vias L32 may be of the order of the thickness L30 of the layer 30, the vias 32 being non-emerging. L32 may be substantially less than or equal to 200 pm, preferably substantially between 50 and 150 pm, for example substantially equal to 100 pm.These length ranges make it possible to facilitate the formation of an electrically conductive or semiconductive through-member, for example a through-interconnection via the via 32, of the substrate 3 during the manufacture of the microelectronic device 4.

[0149] A via 32 may further have several portions each having a configuration, the configurations being different between the portions. For example, a via may have a first portion 32c with one configuration, and a second portion 32d with a different configuration, as illustrated for example in Figures 2A and 2B. The lateral dimension D32 of a via may be different between the portions, for example the first portion 32c and the second portion 32d. In particular, a first portion may be filled and a second portion may be hollow. This makes it possible to obtain a via of smaller dimension while facilitating access through the hollow portion.

[0150] The vias 32 may have a form factor substantially greater than or equal to 5, and preferably greater than or equal to 10. By form factor is meant the ratio between the longest dimension and the shortest dimension. Here the form factor F is such that F = L32 / D32. This form factor makes it easier to form an electrically conductive or semiconducting through member, for example a through interconnection via the via 32, during the manufacture of the device, and to increase the density of the vias 32 on the substrate.

[0151] As illustrated in Figure 2C, a via may have a cross-section, for example in a plane substantially parallel to the main extension plane of the first 30 and second 31 layers, of square, polygonal, or cylindrical shape. Preferably, the vias 32 are cylindrical.

[0152] According to an example illustrated in Figure 2A and 2B, a via 32 may comprise a groove 35 configured to improve the electrical insulation of the vias 32. The substrate 32 is thus particularly suitable for high frequency applications and / or as a replacement for a high resistivity substrate for applications requiring it. For this, the via 32 has a cross-section entirely surrounded by the groove 35, taken in the main extension plane of the first 30 and second 31 layers. The groove 35 may surround the via 32 over at least a portion of its longitudinal dimension L32. The grooves 35 are preferably arranged so as to isolate the vias 32 from each other, a groove 35 preferably surrounding a single via 32. The grooves 35 preferably do not touch each other. The groove 35 may more particularly extend from the second layer 31 over a portion of the first layer 30.Note that groove 35 can be arranged around a via 32 regardless of its configuration described above. The groove provides better dielectric insulation to the via configuration it surrounds.

[0153] Each groove 35 is preferably buried, that is to say that it does not open onto one or other of the exposed surfaces 3a, 3b of the substrate 3. Each groove 35 therefore defines a closed volume. Each groove 35 may be hollow, it is not filled with a solid material. Each groove 35 is then preferably filled with a gaseous atmosphere such as air, nitrogen or argon, possibly at a pressure less than or equal to ambient pressure. Each groove 35 may be filled, preferably entirely, with a solid material, and for example with a dielectric material.

[0154] Each groove 35 may be delimited by a side wall 350, a bottom wall 351 and an upper wall 352 opposite the bottom wall 351. The bottom wall 351 is arranged towards the rear surface 3b of the substrate and the upper wall 352 is arranged towards the front surface 3a of the substrate 3. Among these walls, at least the bottom wall 351 and the side wall 350 may be made of dielectric material, for example SiC>2. As illustrated in FIG. 2A, all the walls may be made of dielectric material. Provision may be made for the groove 35 to be flush with the surface of the first layer 30, like the vias 32 illustrated in FIGS. 2A and 2B. The upper wall 352 may be of the same material as the second layer 31. All the walls may be of the same material as the layer in which or against which they extend, of dielectric, semiconducting or piezoelectric material depending on the layer considered.

[0155] As illustrated for example by figures 2A and 2B, each groove 35 may have a longitudinal dimension, or equivalently a depth, L35 substantially equal to or less than that of the via L32, according to one example equal to plus or minus 5 pm.

[0156] As illustrated for example by Figures 2A and 2B, each groove 35 may have a transverse dimension D35 taken on either side of the via 32, for example a diameter, substantially less than or equal to 50 pm, preferably substantially between 20 pm and 30 pm. Each groove 35 may have a width substantially less than or equal to 5 pm, for example substantially between 2 and 4 pm. Thus, similarly to the dimensions of the vias 32, an improvement in the electrical insulation can be obtained while making it possible to obtain a high density of vias 32. Synergistically, it is particularly advantageous to use these grooves 35 when the vias 32 are close to each other, as is the case for a high density of vias 32 on the substrate 3, in order to improve their electrical insulation. By high density, for example the pitches A and / or B are less than or equal to 100 pm.It can be provided that the grooves 35 have equal or distinct dimensions between the different grooves 35.

[0157] Depending on the dimensions of the grooves 35 in the main extension plane of the first 30 and second 31 layers, the pitch can be adapted so that the grooves 35 are distinct from each other. Each groove 35 can be cylindrical, and preferably concentric with the via 32 which it surrounds.

[0158] When the substrate 3 comprises several assemblies 32a, each assembly may have a via configuration, or where appropriate several sections of configurations. The via configurations 32 of different assemblies 32a may differ from each other. Preferably, each via 32 of the same assembly 32a has the same via configuration, or where appropriate several sections of configurations. The dimensions of the vias 32 may further vary between the different assemblies 32a. Preferably, each via 32 of the same assembly 32a has the same dimensions. The cross-section of the vias 32 may further vary between the different assemblies 32a. Preferably, each via 32 of the same assembly 32a has the same cross-section.

[0159] As illustrated for example in Figures 1A, 1B, and 3A, 3B, the substrate 3 may comprise at least one mark or equivalently a reference mark 34 allowing the alignment of the substrate 3 with other elements. Thus, the placement of the vias 32 during the manufacturing process of the microelectronic device is made more reliable. This reference mark 34 may be formed by one or more portion(s) of layer of dielectric material at the level of the first layer 30 and / or the second layer 31. Note that the person skilled in the art can quite easily envisage other variants of reference mark, such as for example a marking arranged on the front surface 3a or the rear surface 3b of the substrate 3.

[0160] The method of manufacturing the substrate 3 is now described with reference to FIGS. 4A to 5D.

[0161] The method comprises providing a sub-substrate 1. The sub-substrate 1 comprises at least a first layer 10, intended to form the first layer 30 of the substrate 3 which will be obtained, as illustrated for example in FIGS. 4A and 5A. According to an example not illustrated, the sub-substrate 1 may further comprise a surface layer intended to form at least in part the second layer 31 of the substrate 3. The surface layer is preferably based on or made of a dielectric material. The sub-substrate 1 further has an exposed surface 1a, at the level of the first layer 10 or the surface layer 11.

[0162] As for example illustrated by Figures 4A and 5A, the vias 32 can be formed by etching, and preferably by deep reactive ion etching (commonly abbreviated DRIE, from the English “Deep Reactive Ion Etching”). For this, the etching step can comprise the application of a mask 12 comprising openings 120 from which the vias 32 will be etched, as illustrated for example in Figure 5A. The mask 12 is preferably a resin mask. It can be provided that the mask is hard, for example with the application of a resin mask 12 then the etching of the surface layer 11 of dielectric material, removing this mask and etching the first layer 10 using the so-called “hard” oxide mask thus formed. Note that the surface layer 11 can be removed after the etching of the vias 32, and the vias 32 electrically isolated by deposition of a dielectric layer thereafter.

[0163] The etching is preferably configured to obtain the characteristics of the vias 32 described previously, and in particular their dimensions and the pitches separating them. For example, the dimensions of the mask 12 and / or the etching time and speed are adjusted for this.

[0164] The etching is configured to etch only the periphery of the vias 32. As illustrated for example in FIG. 4A, a groove 320' can be etched, this groove 320' being intended to form the side wall 320 of the via 32. Alternatively, as illustrated for example in FIG. 5A, the via 32 can be etched over substantially its entire volume.

[0165] To form the sidewall 320 of dielectric material, the method may then comprise forming a dielectric material to form the sidewall 320. As illustrated for example in FIG. 4B, the groove 320' may be filled, preferably entirely, with a dielectric material. For this, the dielectric material, for example silica SiC>2, may be deposited. This deposition may be a chemical vapor deposition (commonly abbreviated CVD) from gaseous precursors comprising oxygen and silicon, for example tetraethyl orthosilicate (commonly abbreviated TEOS) or silane of chemical formula SihL, optionally combined with dioxygen.The deposition is for example a subatmospheric pressure CVD deposition (commonly abbreviated SACVD, from the English Sub-Atmospheric CVD), or a plasma-enhanced chemical phase deposition (commonly abbreviated PECVD, from the English Plasma-Enhanced CVD).

[0166] When the via 32 is etched over substantially its entire volume, the formation of the dielectric material can be carried out on the side wall 320 and the bottom wall 321, as illustrated for example in FIG. 5B. This formation can be done by deposition of the dielectric material as described above. This formation can alternatively be done by thermal oxidation, for example at a temperature of substantially 1050°C in an atmosphere comprising oxygen.

[0167] Preferably, the formation of the walls 320, 321 is configured so that the walls 320, 321 of dielectric material have a dimension substantially between 50 nm and 600 nm, and preferably substantially equal to 400 nm. For the side wall 320, this dimension is the transverse dimension. For the bottom wall 321, this dimension is the longitudinal dimension. For example, the thermal oxidation time or the deposition time and / or the deposition rate can be adjusted for this.

[0168] When the via 32 is etched over substantially its entire volume, and preferably following the formation of the walls 320, 321 made of dielectric material, the via 32 may be filled with an electrically conductive or semiconductive material 323, as for example illustrated in FIG. 5C. The conductive material may be a metal, for example copper or tungsten. The semiconductive material may be polycrystalline silicon (generally designated Poly-Si). This filling is preferably done by depositing the material 323 in the via 32. For example, the deposition of Poly-Si is generally done by LPCVD (abbreviated from the English Low Pressure Chemical Vapor Deposition, which can be translated as chemical vapor deposition at subatmospheric pressure).

[0169] According to the via formation steps described above, the different configurations of the vias 32 described previously can be obtained. For example, it is possible to move from FIG. 5A to the assembly with the donor sub-substrate 2 to obtain hollow vias 32 without a side wall 320 made of dielectric material. For example, it is possible to move from FIG. 5B to the assembly with the donor sub-substrate 2 to obtain hollow vias 32 with a side wall 320 and a bottom wall 321 made of dielectric material.

[0170] To obtain a via with several portions each presenting a configuration, it is possible to make a combination of etchings and deposition, or even transfer of substrate layer 1 to plug the via in the rear part of the substrate.

[0171] The mask 12 can be removed following the formation of the dielectric material, or even following the filling of the via 32 with the material 323. Alternatively, the mask 12 can be removed prior to the formation of these walls in dielectric material. In the case where the layer 11 has served as a hard mask, it is preferable to remove it as well.

[0172] The method may comprise, concomitantly or following the formation of the vias, a step of forming the mark 34. For this, the mask may further comprise openings, not shown here, for etching, for example, openings in the second layer 31 up to the first layer 30. The openings may be filled with the dielectric material during the formation of the walls. The formation of the mark 34 may be separate from these steps, for example by applying a mask specific to this mark 34, etching and filling the openings. If the formation of the mark 34 is separate from these steps, it is advantageously carried out beforehand, to serve as a reference for the positioning of the vias 32.

[0173] The formation of the grooves 35 may comprise the same steps as for the etching of the vias 32 and, where appropriate, for the formation of the walls made of dielectric material. The grooves 35 may be formed simultaneously with the vias 32, the mask 12 then comprising openings corresponding to the grooves 35 to be etched. The grooves 35 may alternatively be etched before or after the etching of the vias 32, for example by applying a mask and etching specific to the grooves 35. According to one example, once the grooves 35 and vias 32 have been etched, a dielectric material may be formed at the walls 350, 351, 320, 321 as previously described. Alternatively, the grooves 35 can be formed after the formation of the dielectric material at the walls 320 and 321. It can be provided that a new formation of dielectric material is made at the walls 350, 351, according to the methods previously described.The etching of the grooves 35 may otherwise not be followed by a formation of dielectric material at the walls 350 and 351. The grooves 35 and the vias 32 may not have a wall of dielectric material, according to a variant.

[0174] Following the formation of the vias 32 and, where appropriate, the grooves 35, these structures can be covered to be buried during the assembly of the sub-substrate 1 with a donor sub-substrate 2. The method can therefore comprise the provision of a donor sub-substrate 2 having an exposed surface 2a'. The assembly methods described below can be applied to all the examples described previously.

[0175] As for example illustrated by Figure 4D, the support 1 and donor 2 sub-substrates can be assembled by bringing their respective surfaces 1a, 2a into direct bonding contact. The donor substrate 2 can then be thinned, for example by cleavage using the process known as Smart-Cut®.

[0176] The assembly may therefore comprise, before bringing the surfaces 1a, 2a into contact, the formation of a weakening zone 22 at a non-zero depth of the surface 2a of the donor sub-substrate 2. This weakening zone 22 is for example formed by implantation of ions, such as hydrogen and / or helium ions. Note that any other technique for forming a weakening zone, and in particular any other technique used in the methods for producing SOI-type stacks, may be envisaged.

[0177] Following the assembly of the support sub-substrate 1 and the donor sub-substrate 2, the method may comprise the separation of a surface layer of the donor sub-substrate 2, at the weakening zone 22, as illustrated by the transition from FIG. 4D to FIG. 4E. This separation may be carried out thermally or mechanically, according to steps known to those skilled in the art.

[0178] Following separation, the resulting surface 3a may be irregular. Polishing, chemical smoothing or chemical and / or mechanical and / or thermal and / or ion beam healing based on atom clusters or based on monomers of the surface 3a may be carried out, so that the surface 3a has a crystalline quality and a roughness suitable for other subsequent processes. Any chemical mechanical polishing (CMP) or thermal method intended to smooth a surface based on semiconductors and in particular silicon may be considered.

[0179] According to one example, the donor sub-substrate 2 comprises a layer 20 based on or made of a semiconductor material, for example silicon and more particularly monocrystalline silicon, or a piezoelectric material. The donor sub-substrate 2 may further comprise a layer 21 based on or made of a dielectric material, for example silica SiC>2.

[0180] According to one example, the layer 21 based on a dielectric material can form the surface layer of the donor sub-substrate 2. In particular, it is possible to directly bond dielectric material, for example silicon oxide, against a dielectric material, for example silicon oxide. Following their assembly, the layer 21 and the layer 11 will form the second layer 31 of the substrate 3. Their respective thicknesses can therefore be chosen to obtain the desired thickness L31. According to this example, it is understood that the upper wall 322 of the vias 32 and, where appropriate, the upper wall 352 of the grooves 35 can be formed from a dielectric material.

[0181] Alternatively, it is possible in particular to carry out direct bonding of dielectric material, for example silicon oxide, against the semiconductor of layer 10 of the support sub-substrate 1. Following their assembly, layer 21 will form the second layer 31 of substrate 3. According to this example, it is understood that the upper wall 322 of the vias 32 and where appropriate the upper wall 352 of the grooves 35 can be formed from a dielectric material.

[0182] According to one example, the layer 20 can form the surface layer of the donor sub-substrate 2. Direct bonding of dielectric material, for example silicon oxide, against semiconductor or piezoelectric material can be carried out. Following their assembly, the layer 20 will form the second layer 31 of the substrate 3, and an intermediate layer of dielectric is arranged between the first layer 30 and the second layer 31. According to this example, it is understood that the upper wall 322 of the vias 32 and, where appropriate, the upper wall 352 of the grooves 35 can be formed from a semiconductor or piezoelectric material.

[0183] According to one example, the layer 20 can form the surface layer of the donor sub-substrate 2. Direct bonding of semiconductor or piezoelectric against semiconductor, and in particular silicon, can be carried out when the layer 20 is based on a semiconductor or piezoelectric material. Following their assembly, the layer 20 will form the second layer 31 of the substrate 3.

[0184] Note that it is preferable to have a thickness of dielectric material, and in particular oxide, of at least 10 nm at the bonding interface for the assembly to avoid the appearance of defects.

[0185] The method of manufacturing a microelectronic device 4 is now described with reference to FIGS. 6A to 8D.

[0186] In this method, the vias 32 may be used to establish interconnections. The vias 32 may alternatively or additionally be used to form portions of a microelectronic device without necessarily being metallic interconnections, for example in a MEMS device.

[0187] The method may comprise providing the substrate 3. The method may comprise depositing layers of components, for example transistor, diode, memory point. This deposition may for example comprise the steps of FEOL.

[0188] As for example illustrated in Figure 6D, the method may comprise the deposition of at least one portion of layer 40, also called device portion 40, on the front surface 3a of the substrate 3. In the following, it is considered, without limitation, that several portions 40 are deposited. Alternatively or in addition, the device portion(s) may be etched in the front exposed surface 3a of the substrate 3.

[0189] These portions may be metallic 40 and may in particular form metallic interconnection lines. Typically, these metallic portions 40 may be used to redistribute electrical signals. These metallic portions may also be designated metallization levels. There may be several metallic portions 40 with interconnections between these portions. This deposition may, for example, include the BEOL steps.

[0190] In the following, it is considered, without limitation, that these portions 40 are metallic and that the etched via 32 serves to establish an interconnection. The following steps apply entirely to the case where non-metallic portions 40 of device 4 are deposited and / or etched.

[0191] The deposition of at least a portion of layer 40 can be done after the formation of the vias 32 as illustrated, and where appropriate after the formation of the conductive or semi-conductive members 45, or before.

[0192] In order to facilitate the handling of the substrate 3, the method may comprise the mounting of a support 41 on the side of the front surface 3a and / or the exposed rear surface 3a of the substrate 3, depending on the manufacturing steps. This mounting may be done for example by means of a bonding 410, as illustrated by FIG. 6B. This also makes it possible to protect the deposits made on the surface of the substrate 3. The method may further comprise the dismantling of this support 41, for example when it is necessary to access the surface covered by the support 41 or at the end of the process.

[0193] The method comprises etching at least one via 32 in order to provide at least one electrical continuity between a portion 40, the via 32 and the rear surface 3b of the substrate. For this, several examples are possible and are now described. For the sake of simplification of the figures, the portions 40 are not shown in all the figures. In the following, it is considered, without limitation, that several vias 32 are etched.

[0194] Preferably, the method comprises a selection of only a portion of the vias 32, to define a group of vias to be etched 32'. Thus, from the generic substrate 3, only the vias of interest can be used for the manufacture of the microelectronic device 4. In the following, it is considered, without limitation, that the method comprises this selection and that only a portion of the vias 32 are used, and not all of them.

[0195] According to a first example, as illustrated by FIG. 6A to 6D, from the front surface 3a, a cavity 43 can be created to reach the vias 32'. For this, a mask 42 can be applied to the front surface of the substrate 3. The mask can comprise openings 420 or be etched to present the openings 420. The mask can be a hard mask, for example based on or made of SiC>2. The mask is for example deposited by PECVD.

[0196] Cavities 43 may be etched so as to reach the vias 32', and more particularly so as to reach and preferably exceed their upper wall 322, as for example illustrated by FIG. 6A. For this, silicon etching in SFe is for example carried out. Preferably, the etching does not expose the conductive material of the via 32' at this time in order to avoid contamination of the substrate. This could indeed be harmful if active devices are subsequently produced. In order to expose the conductive material 323 of the via, the method may comprise RIE etching (abbreviated from the English Reactive Ion Etching, which can be translated as reactive ion etching) to open the bottom of the cavity, also called "etch back". It is preferable that the electrically conductive material of the via is not exposed until after the formation of the dielectric walls 450, described later.

[0197] Once the cavities 43 are formed, the method may comprise the deposition of an electrically conductive or semiconductive member 45. This member 45 may be based on or made of a metallic material 45, for example electrolytic copper or CVD tungsten. Alternatively, this member 45 may be based on or made of a semiconductive material, for example poly-Si. The deposition may be configured so as to fill these cavities 43 with the metallic material to form an electrical interconnection or a device portion 40, as for example illustrated by FIG. 6D.

[0198] From the rear surface 3b of the substrate 3, the first layer 30 can be etched until it is flush with, or exceeds, the bottom wall 321 of the vias 32. For this, the first layer 30 can be thinned and etched by etching the material of the first layer 30. The entire rear surface 3b of the substrate 3 can be etched. All the vias 32 will thus be reached.

[0199] This etching may, according to one example, be a selective etching of the material of the layer 30 relative to the dielectric material of the walls of the via 32. The etching may, for example, be a selective etching of the silicon relative to the silica SiC>2 in reactive ion etching using a precursor such as SFe. By “selective etching of a material A relative to a material B” is meant that the etching speed of the material A is 10 and preferably 100 times greater than that of the material B. It is also possible to envisage carrying out a partial mechanical thinning of the substrate 3 completed by selective plasma or chemical etching. The wall of dielectric material may then be selectively etched relative to the material of the first layer 30, to open into the via 32'. Only certain vias 32' may be subjected to this selective etching. For example, the etching of the dielectric material may be a reactive ion etching.The etching of the semiconductor material may be similar to that done to etch layer 30.

[0200] Alternatively or in addition, it is also possible to envisage localized etching from the rear surface 3b by means of a mask having openings directly above the vias 32' to be etched, and the filling of the etched cavities with an electrically conductive or semi-conductive member.

[0201] Preferably, prior to the deposition of the electrically conductive or semiconductive member on the front surface 3a and / or rear surface 3b of the substrate 3, the method comprises the formation of a wall 450 made of dielectric material so as to insulate this member from the layers that it passes through, as illustrated in FIG. 6C for example. The walls 450 may be formed by a PECVD deposition, for example of SiC>2. This deposition is preferably sufficiently conformal to cover the sides of the cavity 43. This makes it possible to avoid a short circuit by the substrate 3.

[0202] The method may then comprise a deposition configured so as to cover with a metallic or semiconducting layer 46 at least a portion of the exposed rear surface 3b of the substrate 3, to provide continuity between the device portion 40, the via 32 and the rear face 3b of the substrate 3, as illustrated for example by FIG. 6D.

[0203] The method may further comprise at least one of, preferably between the formation of the cavities 43 and the deposition of the layer 46:

[0204] - the removal of mask 42,

[0205] - a passivation of the exposed rear surface 3b of the substrate 3, for example by forming a layer of dielectric material 44, also called passivation layer 44. This formation can be done by depositing a dielectric material, for example as described previously,

[0206] - etching of layer 44 so as to remove any oxide layer that may have formed at via 32'. This possible oxide layer may in fact limit the resumption of electrical contact on portion 40.

[0207] According to the example illustrated by figure 7, this method can also be applied to a via having a side wall made of dielectric material and filled with the same material as the first layer 30. The same steps as described previously can be applied.

[0208] Figures 8A to 8D describe another example in which the vias 32 are hollow. As previously described, a cavity 43 can be formed directly above the vias to be etched 32', so as to open into the via 32.

[0209] When the walls of the vias 32' to be etched are not made of dielectric material, the method may comprise the formation of a dielectric layer at least at the level of the side wall 320, according to the methods previously described with reference to the method of manufacturing the substrate 3. This example may be illustrated by FIG. 8B. Walls 450 made of dielectric material are further advantageously formed at the level of the etched cavities 43.

[0210] The vias 32' can then be filled with the electrically conductive or semiconductive member 45. The steps described below with reference to the previous examples can be applied.

[0211] Alternatively, the etching can be carried out from one face of the substrate 3 until it opens into the via 32', and continued to form at least one cavity 43, for example an electrical connection cavity 43 and reach the other face of the substrate 3, whether from the front face or the rear face. The method can further comprise the other steps described previously to obtain the device illustrated in FIG. 8D.

[0212] As illustrated by FIGS. 9A to 9C, the examples described may also apply to the example according to which the vias 32 have several configuration sections along the same via 32. For example, a portion filled with an electrically conductive or semiconductive material may be connected by the member 45. A hollow portion of the via 32 may be at least partly filled by the layer 46 and / or another member 45, after formation of a wall of dielectric material so as to insulate the via 32.

[0213] The examples described can also apply to the example according to which the vias 32 comprise grooves 35. In order not to fill the grooves of the conductive or semi-conductive member, the openings 420 of the mask 42 can be arranged so as not to allow the etching of the grooves 35. During the steps subsequent to the formation of the cavities 43, the grooves 35 preferably remain closed and are therefore not filled by the member 45.

[0214] In view of the foregoing description, it is clear that the invention provides a substrate, a method of manufacturing the substrate, and a method of manufacturing a microelectronic device for facilitating the manufacturing of vias in a microelectronic device.

[0215] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention. The present invention is not limited to the examples previously described. Many other variant embodiments are possible, for example by combining features previously described, without departing from the scope of the invention. In addition, the features described in relation to one aspect of the invention may be combined with another aspect of the invention.

[0216] In particular, the substrate may have any characteristic resulting from its manufacturing process and conversely, this process may comprise any step configured to obtain a characteristic of the substrate. The manufacturing process of a microelectronic device may implement any characteristic of the substrate.

[0217] In the examples described, the semiconductor material is silicon. Note that the invention can be applied to other mono- or polycrystalline semiconductors, possibly doped, and in particular to Si, Ge, SiGe, SiC, III-V material (for example AIN, GaN, InN, InGaAs, GaP, InP, InAs, AsGa, etc.) and III-VI material. The dielectric material can be a semiconductor oxide or nitride, for example SiO2, SiN, AI2O3. The piezoelectric material can, for example, be chosen from lithium tantalate (LiTaOs), lithium niobate (LiNbOs), potassium-sodium niobate (K x Nai. xNbOs or KNN), barium titanate (BaTiOs), quartz, lead zirconate titanate (PZT), a compound of lead-magnesium niobate and lead titanate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AIN) or aluminum scandium nitride (AIScN), other materials can of course be considered.

Claims

DEMANDS 1. Substrate (3) comprising: • a first layer (30) based on a semiconductor material, • a second layer (31) layer overlying the first layer (30). characterized in that the substrate (3) comprises a plurality of buried vias (32) extending from the second layer (31) over a portion of the first layer (30), each via (32) being delimited by a side wall (320), a bottom wall (321), and a top wall (322) opposite the bottom wall (321), and in that at least one set (32a) of the plurality of vias (32) forms a pattern (32b) repeating along at least one direction of the main extension plane of the first (30) and second (31) layers.

2. Substrate (3) according to the preceding claim, wherein each via (32) has at least one transverse dimension between 1 pm and 30 pm.

3. Substrate (3) according to any one of the preceding claims, wherein at least a portion of the vias (32) has a form ratio greater than or equal to 10, of longest dimension oriented along a thickness dimension of the first (30) and second (31) layers.

4. Substrate (3) according to any one of the preceding claims, wherein, within a set (32a) of vias (32), two successively repeating patterns (32b) of vias (32) are separated by a constant pitch along at least one direction of the main extension plane of the first (30) and second (31) layers, the pitch being between 50 pm and 300 pm.

5. Substrate (3) according to any one of the preceding claims, wherein the substrate (3) comprises a single set (32a) of vias forming a pattern (32b) comprising a single via (32), each via (32) being separated from the nearest neighboring vias (32) by a constant pitch, along two distinct directions from the main extension plane of the first (30) and second (31) layers.

6. Substrate (3) according to any one of claims 1 to 4, wherein the substrate (3) comprises several sets (32a, 32a', 32a”) of vias (32) each forming a pattern (32b, 32b', 32b”) repeating along at least one direction of the principal extension plane of the first (30) and second (31) layers.

7. Substrate (3) according to any one of the preceding claims, wherein at least one via (32) has at least one via configuration among the following: • the side wall (320) of the via (32) is made of a dielectric material, and the via (32) is filled with an electrically conductive or semiconductive material or the via (32) is hollow, • the side wall (320) of the via (32) is made of a dielectric material, and the via (32) is filled with the material of the first layer (30), • the side wall (320) of the via (32) is made of the material of the first layer (30) and the via is hollow.

8. Substrate (3) according to the preceding claim, wherein at least one via (32) has a first via configuration on a first portion (32c), and a second via configuration distinct from the first via configuration on a second portion (32d), the first (32c) and second (32d) portions extending successively along a thickness dimension of the first (30) and second (31) layers.

9. Substrate (3) according to any one of the two preceding claims in combination with claim 6, wherein at least one set (32a, 32a', 32a') has at least one via configuration distinct from another set (32a, 32a', 32a').

10. Substrate according to any one of the preceding claims, wherein the pattern (32b) of at least one set (32a) is repeated along at least one direction of the principal extension plane of the first (30) and second (31) layer, over at least 80% of one dimension of the substrate (3) along that direction.

11. A method for manufacturing the substrate (3) according to any one of the preceding claims, comprising: • a supply of a support sub-substrate (1) comprising at least a first layer (10) based on a semiconductor material, the support sub-substrate (1) having an exposed surface (1a), • the formation of a plurality of vias (32) such that the vias (32) extend from the exposed surface (1a) over a portion of the first layer (10), each via being delimited by a lateral wall (320) and a bottom wall (321), at least one set (32a) of vias (32) forming a pattern (32b) repeating along at least one direction of the main extension plane of the first (30) and second (31) layers, • a supply of a donor sub-substrate (2) comprising a surface layer (20, 21) having an exposed surface (2a), • an assembly of the support sub-substrate (1) and the donor sub-substrate (2) by their exposed surfaces (1a, 2a), so as to cover the vias (32), each via then being delimited by the side wall (320), the bottom wall (321), and a top wall (322) opposite the bottom wall (321).

12. Method according to the preceding claim wherein the formation of the plurality of vias (32) comprises, for at least one set of vias (32a) and on at least a first portion (32c) of said vias (32), an engraving of at least one perimeter of the via (32).

13. Method according to the preceding claim, wherein the formation of the plurality of vias (32) comprises, following the engraving at least of the periphery of the via (32), a formation of a dielectric material on at least the engraved periphery of the via (32) so as to form the lateral wall (320) of the via (32) in dielectric material.

14. Method according to the preceding claim, wherein during the engraving of at least the periphery of the via (32), the via (32) is engraved over substantially its entire volume, and the formation of the plurality of vias (32) comprises, following the formation of a dielectric material on at least the engraved periphery of the via (32) so as to form the lateral wall (320) of the via (32) in dielectric material, a deposit of an electrically conductive or semiconducting material (323) so as to fill at least part of the via.

15. Method according to any one of the four preceding claims, the formation of the plurality of vias (32) comprises the formation of several sets (32a, 32a', 32a”) of vias (32) each forming a pattern (32b, 32b', 32b”) repeating along at least one direction of the principal extension plane of the first (30) and second (31) layers, 16. Method for manufacturing a microelectronic device (4) comprising: • a supply of a substrate (3) according to any one of claims 1 to 10 and / or a substrate (3) manufactured by the process according to any one of claims 11 to 15, having a front exposed surface (3a) and a rear exposed surface (3b), • the formation of at least one portion of a layer (40) of the device (4) by depositing said portion onto at least one of the front (3a) or rear (3b) exposed surfaces of the substrate (3), and / or etching at least one of the front (3a) or rear (3b) exposed surfaces of the substrate (3), configured to form said portion (40), at at least one via, etch through one of the exposed front (3a) or rear (3b) surfaces of the substrate (3), until the via is reached, and: o continue etching to reach at least one portion of the layer (40) of the device (4), or o at at least one via, etch through the other of the exposed front (3a) or rear (3b) surfaces of the substrate (3), until the via is reached, • the deposition of at least one electrically conductive or semiconductive element (45) so as to put in electrical continuity at least the via (32) and the portion of device layer (40).

17. Method according to the preceding claim, wherein the method comprises, a selection of at least one via to be engraved (32') from the plurality of vias (32), only a part of the plurality of vias (32) being selected as via to be engraved (32').

18. Method according to the preceding claim, wherein the selection of the at least one via to be etched (32') comprises the application, on said front (3a) or rear (3b) exposed surface of the substrate (3), of a mask (42) comprising openings (420) located in line with the at least one via to be etched (32'), followed by etching so as to reach the at least one via to be etched (32').

19. A method according to any one of the two preceding claims, wherein, when the method involves etching by the other among the front (3a) or rear (3b) exposed surfaces of the substrate (3), until the via is reached, the selection of the at least one via to be etched (32') from among the plurality of vias (32) includes the application, on said other front (3a) or rear (3b) exposed surface of the substrate (3), of a mask (42) comprising openings (420) located in line with the at least one via to be etched (32'), and the method further includes an etching so as to reach the at least one via to be etched (32').

20. A method according to any one of the four preceding claims, wherein the deposit of the electrically conductive or semiconductive element (45) is configured so as to further cover with an electrically conductive or semiconductive layer (46) at least a portion of the exposed front (3a) and / or rear (3b) surface of the substrate (3).