METHOD FOR MANUFACTURING SEMICONDUCTOR DISCS

Abstract

The invention relates to a method for producing semiconductor wafers, wherein a monocrystalline rod of silicon is provided, the rod is sliced into crystal pieces and a test wafer is cut from a crystal piece, wherein the test wafer optionally undergoes a first thermal treatment process and then a second thermal treatment process that includes a heating phase, a holding phase at a holding temperature Th and a cooling down phase and causes a radial temperature gradient ∆T on the test wafer, the wafer made of semiconductor material is subsequently inspected for stress fields, and the semiconductor wafers obtained from the crystal piece are processed further in accordance with further processing steps which are selected on the basis of the result of the inspection of the test wafer.

Description

[0001] Methods for manufacturing semiconductor wafers

[0002] The present invention relates to a method for producing semiconductor wafers, in particular the testing of crystal pieces for suitability in the component manufacturing process.

[0003] Monocrystalline semiconductor wafers are the foundation of modern electronics. During the manufacturing of components on these semiconductor wafers, thermal processes are carried out, involving increasingly complex coating steps. It is not surprising that this can lead to thermal stresses (hereinafter referred to as stress) in the crystal lattice. Unfavorable storage of the semiconductor wafers during the thermal treatment can also lead to additional stress, and finally, among other reasons, the coating of the semiconductor wafers itself can also generate additional stress fields.

[0004] The so-called Upper Yield Stress x Uy The upper yield stress is the material parameter of the semiconductor wafer that indicates the stress level at which the wafer is no longer elastically reversible but plastically irreversible. The upper yield stress of an individual semiconductor wafer depends on many parameters that are not, or only partially, accessible or known in any given case.

[0005] If the induced stress is greater than the respective upper yield stress, it can be reduced by irreversible deformations, including the formation of retinal vein occlusions (so-called slip lines), which can lead to failures during the component manufacturing process and thus to increased costs for component manufacturers.

[0006] Monocrystalline semiconductor wafers, especially silicon wafers, are typically manufactured by first drawing a monocrystalline rod using the so-called float zone (FZ) or Czochralski (CZ) process. The rods produced in this way are cut into crystal pieces, which are usually processed into semiconductor wafers using a wire saw or internal hole saw. After grinding, polishing, and edge finishing, an epilayer can optionally be applied using CVD. These semiconductor wafers are then made available for further device manufacturing. If, during the thermal treatment of the semiconductor wafer in the device manufacturing process, it is only discovered that the wafer is slipping, significant costs can arise, depending on the respective manufacturing depth.

[0007] For this reason, there is a need to only introduce semiconductor wafers into the component manufacturing process where the stress occurring during the component manufacturing process is less than the upper yield stress, thus preventing the formation of delaminations and therefore defects.

[0008] In practice, neither the upper yield stress of the respective semiconductor wafer nor the stress occurring during the component manufacturing process is sufficiently known.

[0009] The stress occurring in the semiconductor wafer during a thermal step can, in principle, be reduced. For example, US 2007 / 084827 A1 teaches that a susceptor with a particularly low surface roughness, on which the semiconductor wafer is placed during thermal treatment, is suitable for reducing the number of gliding events. However, this measure generally does not prevent the reduction of thermally induced stress, such as that caused by very high heating and cooling rates. In practice, high heating and cooling rates are common because high throughput limits the available time.

[0010] US Patent 2004 / 040632 A1 describes a special susceptor that provides a flat contact surface for semiconductor wafers for high-temperature treatment. This susceptor appears suitable for reducing mechanically induced stresses in the semiconductor wafers during treatment. However, thermally induced stresses are not reduced.

[0011] Both the upper yield stress of a semiconductor wafer and the actual stress induced in the semiconductor wafer during the device manufacturing process are very difficult to predict. Consequently, it is also very difficult to predict whether a semiconductor wafer will be damaged during the device manufacturing process.

[0012] Therefore, a first object of the present invention is to provide a method for evaluating semiconductor material of a semiconductor wafer that can provide an indication of whether the manufactured semiconductor wafers are damaged by slippage during the component manufacturing process or not.

[0013] A second object of the present invention is to provide a method for evaluating a semiconductor wafer that can determine the magnitude and direction of a residual voltage of a wafer.

[0014] The tasks are solved by the characteristics of the claims.

[0015] Preferred embodiments of the method according to the invention are described in detail below. The individual features can be implemented either separately or in combination as embodiments of the invention.

[0016] The invention is based on a single crystal (rod, ingot) of silicon grown according to the prior art, which is first cut into crystal pieces by means of a saw, preferably a band saw.

[0017] For the invention, the single crystal can also consist of a different semiconductor material such as germanium, gallium arsenide, gallium nitride, or mixtures thereof. Furthermore, in addition to the Czochralski crystal-pulling method, other crystal-growing methods such as float zone (FZ) can also be used for the invention.

[0018] Preferably, at least one semiconductor wafer is cut from a crystal fragment as a test wafer using a band saw or internal hole saw and subjected to the investigation according to the invention. The corresponding remaining crystal fragment is then used in the further manufacturing process for semiconductor wafers, depending on the results of the investigation.

[0019] The further manufacturing process for semiconductor wafers includes the steps of wire sawing, grinding, lapping, polishing, edge rounding, cleaning, and etching. The application of a homo- or hetero-epitactically deposited layer of additional semiconductor material is optional.

[0020] The semiconductor wafers separated from a single crystal are preferably a monocrystalline silicon wafer with a diameter of 150 mm, 200 mm or preferably 300 mm.

[0021] A semiconductor wafer comprises a front and a back surface, as well as a circumferential edge, which together form the surface of this wafer. The edge typically consists of two flattened surfaces, called facets, created through prior grinding and etching processes, and a circumferential surface perpendicular to the front and back surfaces of the wafer, respectively, called the apex or blunt. By definition, the front surface of the semiconductor wafer is the surface on which the desired microstructures are applied in subsequent device manufacturing processes.

[0022] According to the invention, the semiconductor wafer thus obtained is preferably subjected to a first thermal treatment, wherein the thermal budget of this thermal treatment preferably corresponds to the thermal treatment in the device manufacturing process. It is irrelevant for the invention whether this first step is carried out. However, the inventors have recognized that carrying out this step significantly improves the measurement results.

[0023] In the electronic component manufacturing process, thermal treatment steps are typically performed, for example, to apply coatings. Depending on the type of coating, different thermal conditions such as temperature and time (thermal budget) and different gas compositions (ambient) are required. It was found that for the method according to the invention, it is irrelevant whether a layer is deposited during the thermal treatment or not. It is apparently sufficient to mimic the essential time-temperature profile (thermal budget) during the electronic component manufacturing process.

[0024] One such component manufacturing process could be the so-called Toshiba test (3 hours at 780°C, followed by 16 hours at 1000°C). However, other thermal steps can also be used.

[0025] If, in addition, the atmosphere mainly used in the component manufacturing process is preferably used in the first thermal treatment step, the results of the process according to the invention are significantly improved again. The atmosphere preferably contains one or more gases from the group consisting of He, Ar, H₂, O₂, N₂, NH₃, SiHC, SiH₂Cl₂, SiH₂, SiCU, CH₄Cl₂S₂, CH₄, or H₂O.

[0026] The second thermal treatment process includes a heating phase, a holding phase, and a cooling phase. The heating phase is the phase in which the semiconductor wafer is heated from room temperature to the desired holding temperature Th.

[0027] The heating rate is defined as the quotient of the temperature difference between room temperature and the temperature during the holding phase and the time required for heating. Similarly, the cooling rate is defined as the quotient of the temperature difference between the temperature during the holding phase and room temperature and the time required for cooling.

[0028] A cooling rate of no more than 4 K / s is particularly preferred. The preferred heating rate is preferably no more than 3 K / s.

[0029] The second thermal treatment process is carried out according to the invention such that a temperature difference is induced on the semiconductor wafer during the holding phase. This temperature difference is defined as a temperature gradient from the center to the edge of the semiconductor wafer, and the average temperature of the semiconductor wafer is understood as the holding temperature.

[0030] A holding temperature between 700°C and 1410°C is preferred (especially between 900°C and 1100°C). The holding time can vary between 10 seconds and 10 minutes; a preferred holding time is approximately 60 seconds.

[0031] The magnitude of the temperature gradient during the holding phase is particularly preferably between 1 and 30 K, and most preferably between 2 and 5 K.

[0032] The magnitude of the temperature gradient is particularly preferred in the holding phase, being higher than in both the heating and cooling phases.

[0033] Several methods are known to those skilled in the art for measuring the temperature gradient. For example, the temperature difference at various points on the hot wafer can be directly determined using one or more pyrometers. However, the set temperature gradient can be determined more precisely indirectly by coating a wafer, for example with SiHCte. The deposition is reaction-limited, so that the deposition rate is a strong function of the temperature. After measuring the thickness of the deposited layer (for example, using ellipsometry) and using suitable calibration curves, the temperature at each point on the wafer can be assigned a specific temperature, and thus the radial temperature gradient can be determined.

[0034] Stress fields are local or global strains in the crystal lattice that can be detected using suitable methods, such as SIRD (Scanning Infrared Depolarization). SIRD utilizes the physical principle that linearly polarized light undergoes a change in polarization direction when it passes through a region under mechanical stress. Depolarization is defined as...

[0035] where lp represents the intensity of the laser light captured by the detector and polarized according to the original polarization direction (i.e., parallel). Io represents the intensity of the laser light captured by the detector orthogonally to the original polarization direction. The degree of depolarization D is considered a measure of the stress in the semiconductor wafer at the measured location.

[0036] The SIRD measurement method is preferred for measuring the voltage in the test disk.

[0037] Preferably, the degree of depolarization is measured at positions within a predefined area of ​​the semiconductor disk in order to obtain position-related measured values.

[0038] The position-related measured values ​​obtained in this way are subjected to a high-pass filter with a cutoff wavelength of 2 mm.

[0039] Subsequently, the standard deviation of these position-related measurements s is calculated.

[0040]

[0041] calculated, where n is the number of measurements, x t for the individual measured value at position i and x for the arithmetic mean of all measured values ​​in said area.

[0042] Preferably, in a first computational method, a region is defined as a radially symmetric ring on the wafer, the center of which coincides with the center on the surface of the wafer. The outer radius of the region is smaller than the radius of the wafer, preferably less than 98% of the radius of the wafer, and the inner radius is greater than 50% of the radius of the wafer, preferably greater than 75% of the radius of the wafer.

[0043] The parameter s determined in this way is understood as the first measure of the robustness of the wafer with respect to a thermal process step in the component manufacturing process.

[0044] For example, the first computational method can be used to examine crystal samples from different crystals whose production processes differ. In this way, parameters of the crystal drawing process can be modified appropriately to meet the stress robustness requirements of the semiconductor wafers.

[0045] In a second calculation method, the measurement data processed with the high-pass filter are divided into at least two regions. Within each region, the maximum and minimum values ​​of the measured value are searched for. If the maximum value is greater than a predefined discriminator value DU and the minimum value is less than the negative value of the discriminator value DU, the region is considered "poor"; otherwise, it is considered "good".

[0046] In this second method, the proportion of good regions relative to all regions is understood as a measure of the semiconductor wafer's susceptibility to stress related to thermal treatment. For example, the second computational method can be used to identify or observe areas that are prone to stress-related robustness.

Claims

Patent claims 1. Method for manufacturing semiconductor wafers, wherein a single-crystal rod made of silicon is provided, the rod cut into crystal pieces and A test disc is cut from a piece of crystal, where the test disc is optionally subjected to a first thermal treatment process and then a second thermal treatment process takes place, which includes a heating phase, a holding phase at holding temperature Th and a cooling phase and this causes a radial temperature gradient DT on the test disk, followed by an examination of the disk made of semiconductor material with regard to stress fields and The further processing of the semiconductor wafers obtained from the crystal piece according to further processing steps that are selected depending on the result of the examination of the test wafer.

2. The method according to claim 1, characterized in that, The temperature of the holding phase Th is between 700°C and 1410°C, preferably between 900°C and 1100°C.

3. Method according to one of the preceding claims, characterized in that the single-crystal rod is drawn according to the Czochralski method.

4. Method according to one of the preceding claims, characterized in that the single-crystal rod is drawn using the float zone method.

5. Method according to one of the preceding claims, characterized in that the heating rate of the heating phase is less than 4 K / s and the cooling rate of the cooling phase is less than 5 K / s.

6. Method according to one of the preceding claims, characterized in that the magnitude of the temperature gradient in the holding phase is between 1 K and 30 K, preferably between 2 K and 5 K.

7. A method according to one of the preceding claims, characterized in that the atmosphere of at least one thermal treatment step contains at least one chemical substance from the list He, Ar, H2, O2, N2, NH3, CH4, SiHCte, SiH Cl2, SiH , SiCU, CH Cl2Si, H2O contains.

8. Method according to one of the preceding claims, characterized in that The investigation of the semiconductor material disk with regard to stress fields includes a SIRD measurement.

9. Method according to one of the preceding claims, characterized in that The magnitude of the radial thermal gradient is smaller in both the heating and cooling phases than the magnitude of the radial thermal gradient in the holding phase.

10. Method according to one of the preceding claims, characterized in that The temperature of the edge of the semiconductor wafer during the holding phase is higher than the temperature in the center.

1. A method according to one of the preceding claims, characterized in that For the second thermal treatment step, a susceptor is used in which the semiconductor disk rests on the entire surface.

12. Method according to one of the preceding claims, characterized in that The duration of the holding phase is at least 10 seconds.