CONTINUOUS TRANSMISSION MESH INTERFACE

Abstract

Continuous transmission mesh interface. The present invention relates to an interface for coupling an agent to a mesh that supports a load / store interconnection protocol and includes a header channel deployed in a first subset of a plurality of physical lanes, wherein the first subset of lanes includes first lanes for loading a packet header based on the interconnection protocol and second lanes for loading metadata for the header. The interface further includes a data channel deployed in a second separate subset of the plurality of physical lanes, wherein the second subset of lanes includes third lanes for loading a packet payload and fourth lanes for loading metadata for the payload.

Description

1 / 128 CONTINUOUS TRANSMISSION MESH INTERFACE RELATED ORDERS

[0001] This application claims the benefit of Provisional Patent Application Serial No. U.S. 62 / 944,207, filed December 5, 2019, the disclosure of which is considered a part of, and is incorporated by reference in its entirety into, the disclosure and this application. FIELD OF THE INVENTION

[0002] This invention relates to computer systems and, in particular (but not exclusively), to point-to-point interconnections. HISTORY

[0003] Advances in logic design and semiconductor processing have allowed an increase in the amount of logic that can be present in integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logic processors in individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logic processors, interfaces, memory, controller hubs, etc. H&áççsto8í7IH»12M^ 2 / 128

[0004] As a result of the increased ability to pack more processing power into smaller packages, smaller computing devices have seen a surge in popularity. Smartphones, tablet computers, ultra-thin notebook computers, and other user equipment have grown exponentially. However, these smaller devices are dependent on servers for both data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e., server space) has also increased. For example, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also called multiple sockets) to increase computing power.But as processing power grows along with the number of devices in a computing system, communication between sockets and other devices becomes more critical.

[0005] In fact, interconnects have grown from more traditional multi-drop buses that primarily handled electrical communications to fully developed interconnect architectures that facilitate fast communication. Unfortunately, as the demand for future processors for even higher consumption rates increases, a corresponding demand is placed on the capabilities of existing interconnect architectures. H&áççstoSÍTIEWE™^ 3 / 128 BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a simplified block diagram illustrating an exemplary embodiment of a system-on-a-chip (SoC) device.

[0007] Figure 2 is a simplified block diagram of a continuous transmission mesh interface.

[0008] Figure 3 is a simplified block diagram of another exemplary continuous transmission mesh interface.

[0009] Figure 4 is a simplified block diagram illustrating an exemplary Compute Express Link (CXL) topology.

[0010] Figure 5 is a simplified block diagram of channels for an exemplary continuous transmission mesh interface.

[0011] Figure 6 is a simplified block diagram illustrating an exemplary receiver temporary storage.

[0012] Figure 7 is a representation of example fields in metadata for a header channel of a continuous transmission mesh interface.

[0013] Figure 8 is a timing diagram that illustrates an exemplary data flow in a header channel of an exemplary continuous transmission mesh interface.

[0014] Figure 9 is a timing diagram that illustrates an exemplary data flow in a data channel of an exemplary continuous transmission mesh interface. Petition 870260023612, dated 03 / 23 / 2026, page 13 2611 4 / 128

[0015] Figure 10 is a diagram illustrating an exemplary initialization state machine for an exemplary flexible matrix mesh interface.

[0016] Figure 11 is a timing diagram that illustrates the initialization of an exemplary flexible matrix mesh interface.

[0017] Figure 12 is a timing diagram that illustrates a first example of a disconnect flow in an exemplary flexible matrix mesh interface.

[0018] Figure 13 is a timing diagram illustrating a second example of a disconnect flow in an exemplary flexible matrix mesh interface.

[0019] Figures 14A and 14B are flow diagrams that illustrate exemplary techniques for signaling using an exemplary continuous transmission mesh interface for load / store protocols.

[0020] Figure 15 illustrates one embodiment of a block diagram for a computing system that includes a multi-core processor.

[0021] Figure 16 illustrates another embodiment of a block diagram for a computing system that includes a multi-core processor.

[0022] Figure 17 illustrates one embodiment of a block diagram for a processor. Petition 870260023612, dated 03 / 23 / 2026, page 11 2611 5 / 128

[0023] Figure 18 illustrates another embodiment of a block diagram for a computing system that includes a processor.

[0024] Figure 19 illustrates one embodiment of a block for a computing system including multiple processors.

[0025] Figure 20 illustrates an exemplary system deployed as a system on a chip (SoC). DETAILED DESCRIPTION

[0026] The following description presents numerous specific details, such as examples of specific processor types and system configurations, specific hardware structures, specific architecture and microarchitecture details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor processing channel stages and specific operation, etc., in order to provide a complete understanding of the present disclosure. It will be evident, however, to a person skilled in the art that these specific details need not be employed in order to practice the embodiments of the present disclosure.In other cases, well-known methods or components, such as alternative and specific processor architectures, specific logic code / circuits for described algorithms, specific firmware code, specific interconnection operation, specific logic configurations, specific materials and manufacturing techniques, and deployments of... Petition 870260023612, dated 03 / 23 / 2026, page 151611 6 / 128 specific compiler, specific expression of algorithms in code, specific switching logic / technique and power reduction, and other specific computer system operational details that have not been described in detail so as to avoid unnecessarily concealing the present disclosure.

[0027] Although the following embodiments may be described with reference to configurability and efficient high-speed data transmission in specific integrated circuits, such as computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and instructions of embodiments described herein may be applied to other types of semiconductor circuits or devices that may also benefit from improved energy efficiency and energy conservation. For example, the embodiments disclosed may be applied to embedded computing systems such as servers, sheets, desktop computer systems, system-on-a-chip (SoC) devices, portable devices, converter-type computers, in-vehicle computing systems, computer vision systems, gaming systems, machine learning systems, and embedded applications.As will be readily apparent from the description below, the types of methods, apparatus, and systems described herein (with reference to hardware, firmware, software, or a combination thereof) are beneficial to the development of... Petition 870260023612, dated 03 / 23 / 2026, page 16 / 263 7 / 128 High-performance computer interconnections and their respective systems.

[0028] As computing systems advance, the components in this document become more complex. As a result, the interconnection architecture for coupling and communicating between components is also increasing in complexity to ensure that bandwidth requirements are met for optimal component operation. Additionally, different market segments require different aspects of interconnection architectures to suit market needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Still, it is a singular purpose of most meshes to provide the highest possible performance with maximum power savings. Below, several interconnections are discussed that would potentially benefit from the aspects of the solutions described in this document.

[0029] An example of an interconnect mesh architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to operate together in an open architecture, spanning multiple market segments; clients (desktop and mobile computers), servers (standard and enterprise), and communication and embedded devices. PCI Express is a general-purpose, high-performance I / O interconnect. Petition 870260023612, dated 03 / 23 / 2026, page 13 / 263 8 / 128 performance defined for a wide variety of future communication and computing platforms. Some PCI attributes, such as its usage model, loading and storage architecture, and software interfaces, have been maintained through its revisions, while previous parallel bus deployments have been replaced by a completely serial and highly scalable interface. The latest versions of PCI Express leverage advances in point-to-point interconnects, switching-based technology, and packet protocol to deliver new levels of performance and features. Power management, Quality of Service (QoS), Hot-Plug / Hot-Swap support, data integrity, and error handling are among some of the advanced features supported in PCI Express.

[0030] Traditional continued transmission interfaces for coupling mesh to protocol agents generally included proprietary interfaces (e.g., Intel™ System-on-Chip Mesh (IOSF™)), interfaces developed for coherent or unordered protocol, and other interfaces that are unsatisfactorily scaled to handle evolving data rates in modern protocols and architectures. For example, proprietary interfaces may carry use-case specific or customized features or information that prevent interface standardization or fail to scale to next-generation bandwidths. While another traditional interface might be defined in a more generic way, for example, as a Petition 870260023612, dated 03 / 23 / 2026, page 18 2611 9 / 128 data bus for carrying packets. However, traditional bus interfaces and definitions can lead to receiver decoding complexity, particularly in the presence of multiple flow control classes or virtual channels, especially as data rates increase and more packets are capable of being processed per clock cycle. As an example, if four (or even more) packets from any flow control or channel can potentially arrive in a given clock cycle, and these are accessing shared temporary stores, then four (or more) corresponding logical write ports may need to be provided at the receiver, resulting in excessive surface area dedicated to providing such logic (and temporary stores).In some instances, traditional interfaces address use cases where multiple packets per cycle (of different flow control classes) are simply stamped with multiple copies of the interface (e.g., one for each flow control class), leading to high pin counts. Additionally, traditional continuous transmission interfaces have header and data packets following each other on the same physical wires, limiting the potential for latency optimizations. Some traditional interfaces fail to provide effective flexible mechanisms for credit flows, among other illustrative disadvantages.

[0031] In some deployments, an enhanced scalable continuous streaming interface may be Petition 870260023612, dated 03 / 23 / 2026, page 19 2611 10 / 128 defined between agent logic on a device and a mesh, such as between the protocol layer and other devices coupled to a mesh (e.g., a CPU, endpoint device, switch, etc.). The continuous streaming interface can support a load / store protocol, such as PCIe, Compute Express Link (CXL) (e.g., CXL.io), among other load / store protocols. The enhanced continuous streaming interface can define interface rules and interface channels to enable significant latency and chip area advantages during deployment, while also providing the power-efficient bandwidth scaling advantages that will become even more critical, particularly as protocols address higher speeds, such as the move to 32.0 GT / s in PCIe Gen 5, or to Data Rates of 64.0 GT / s beyond the initial with PCIe Gen 6 and CXL 3.0, among other examples.Such an interface can optimize the best balance of pin count versus receiver decoding complexity. In some deployments, the enhanced continuous transmission interface discussed in this document may allow a modest number of logical write ports in receiver temporary stores, where the receiver temporary stores are shared among multiple virtual channels and flow control classes. Furthermore, an enhanced continuous transmission interface can bifurcate the packet header and data into independent physical channels. Petition 870260023612, dated 03 / 23 / 2026, page 20 / 263 11 / 128 (for example, a header channel and a data channel) to allow the receiver to begin processing headers while data is still in continuous transmission, thus helping to reduce overall latency and temporary storage scaling and complexity. Furthermore, the improved continuous transmission interface discussed in this document can be standardized to allow IP block ecosystems to adopt and develop a scalable standardized interface instead of traditional proprietary interfaces, and to allow for more interoperability options, among other exemplary features and advantages, as discussed in this document.

[0032] Referring to the simplified block diagram 100 in Figure 1, a simplified example of a system-on-a-chip (SoC) device 105 is illustrated. An SoC can be deployed as an integrated circuit incorporating multiple computer components, or computing blocks (or intellectual property (IP) blocks). Such blocks (e.g., 110, 115, 120, 125, 130, 135, 140, 145) may include components such as one or more CPU components 110, 115, 120, 125 (e.g., a microprocessor or microcontroller), special-purpose processors 130, 135 (e.g., graphics processing units (GPUs), image signal processors (ISPs), tensor processing units, accelerator devices, etc.), memory components, input / output (I / O) ports, secondary storage blocks Petition 870260023612, dated 03 / 23 / 2026, page 18 2611 12 / 128 and other computing blocks on a single die or substrate, such as a silicon die.

[0033] The compute blocks (e.g., 110, 115, 120, 125, 130, 135, 140, 145) of an exemplary SoC 105 can be interconnected by a SoC mesh (e.g., 150). The mesh 150 can be deployed using a set of one or more IP blocks that facilitate communication between the compute blocks (e.g., 110, 115, 120, 125, 130, 135, 140, 145). In some deployments, the mesh 150 can be deployed as a network-on-a-chip (NOC), such as a NOC, deployed on one or more circuit-set blocks.

[0034] Communication between the various blocks (e.g., 110, 115, 120, 125, 130, 135, 140, 145) can be facilitated through protocol agents (e.g., 160a-h) provided in the blocks (e.g., 110, 115, 120, 125, 130, 135, 140, 145). Each agent (e.g., 160a-h) may include logic (e.g., deployed in a set of hardware circuits, firmware, and / or software) to deploy all or a subset of the layers of one or more interconnection protocols (e.g., PCIe, Compute Express Link (CXL), Gen-Z, OpenCAPI, Matrix Interface, Cache Coherent Interconnect for Accelerators (CCIX), UltraPath Interconnect (UPI), etc.) through which the corresponding compute block is to communicate with other compute blocks in the system. As discussed in this document, agents may couple to the 150 mesh via a respective interface. While such agents may have traditionally been coupled to Petition 870260023612, dated 03 / 23 / 2026, page 29 / 264 13 / 128 meshes via patented wire interfaces, one or more agents (e.g., 160a-h) can utilize their respective instances of a configurable flexible array wire interface, which can be installed to support multiple different protocols from multiple different agents of the 105 SoC. In other instances, the interfaces between agents (e.g., 160a-h) can be to support non-coherent streaming and / or load / store protocols, and streaming mesh interfaces can be defined and deployed on blocks (e.g., 110, 115, 120, 125, 130, 135, 140, 145) and mesh 150, among other exemplary deployments.

[0035] As introduced above, an enhanced Continuous Transmission Mesh Interface (SFI) architecture can be provided in the components of a system (e.g., IP blocks and components that deploy the system mesh) to map Load / Store protocols (e.g., PCIe, CXL.io) between an agent and a mesh. An SFI interface can provide a scalable continuous transmission interface that can support the high bandwidth demands of load / store protocols, including emerging next-generation speeds for such protocols. An SFI interface can enable easy deployment on both the transmit and receive sides when transmitting such high data rates. Additionally, the logic that deploys the SFI interface can incorporate, effect, and enforce rules for communications on the interface. Petition 870260023612, dated 03 / 23 / 2026, page 20 / 263 14 / 128 (for example, in addition to those defined in the protocols supported by the interface) to significantly simplify storage overhead in the context of read / write ports on the receiver, among other illustrative advantages.

[0036] An SFI interface can be employed both in the context of a host CPU (e.g., through the root complex) and in the context of a device endpoint. In both cases, SFI serves to carry protocol layer (transaction layer) specific information between different processing entities. As an example, on the device side, SFI can be used to interface between the PCIe controller and the application layer (e.g., the mesh or a gasket layer between the controller and the mesh). Similarly, on the host side, SFI can be used to interface between the PCIe Root Port and the CPU mesh. Configurable parameters can be defined on an SFI interface to allow instances of the interface to be parameterized to be broad enough and carry multiple packets in a single transfer according to the supported protocols and the system use case(s).In a given SFI interface, data transfer can be unidirectional. Consequently, in some deployments, a pair of SFI interface instances may be provided (one in each direction) to facilitate deployments using bidirectional data transfer between communication blocks. Therefore, many of the examples in... Petition 870200023618, dated 03 / 23 / 2026, p. 24 / 264 15 / 128 This document discusses a transmitter (TX) and receiver (RX) pair for a single instance of an SFI interface.

[0037] Different configurations can be made possible by using SFI as the intermediate interface. For example, an SFI interface cannot make any assumptions about specific protocol or application responsibilities of the interface transmitter and receiver. Instead, an SFI interface can simply provide a mechanism and rules for high-bandwidth packet transfer. For example, Figure 2 is a simplified block diagram 200 illustrating an exemplary deployment that couples a controller 210 (e.g., an agent) to an application layer 215 (e.g., deployed through a mesh) via two instances of SFI interface 205a, 205b. The controller 210 may include the set of protocol circuits or other logic to establish a link 220 according to a particular interconnection protocol (e.g., PCIe) and participate in initialization, training, and communications across the link 220.The example in Figure 2 can represent an illustrative use case of SFI in a PCIe application. The SFI instance 205a can treat the PCIe controller 210 as the transmitter and the application layer element 215 as the receiver. Consequently, the application layer element 215 can include a temporary receiver storage for the SFI interface 205a for use in maintaining flow control credits (including credits). Petition 870260023612, dated 03 / 23 / 2026, page 22 / 264 16 / 128 shared for the SFI interface channels 205a). Similarly, the SFI interface 205b can consider the application layer element 215 as the transmitter and the PCIe controller 210 as the receiver (and the controller 210 can include corresponding temporary stores or receiver queues 225 for use with the interface 205b).

[0038] Although some SFI deployments may utilize semantics and header formats from a PCIe-based protocol, SFI is not limited to the supported PCIe-based protocol. Furthermore, SFI does not contain a new protocol definition. SFI semantics can be used to support a variety of different protocols, provided the protocol is mapped to or adapted to the flow control (FC) and virtual channel (VC) semantics that SFI provides, among other exemplary features. For example, SFI supports advertising of 0 or more shared credit groups to receiver queues (as discussed in more detail below).

[0039] Referring to Figure 3, a simplified block diagram 300 is shown that illustrates a traditional complex root stack using an SFI interface. For example, SFI interfaces 205a, 205b can be used to couple protocol stack logic (e.g., 305, 310) to a non-coherent-to-coherent protocol converter 315 (e.g., which can be established between the protocol stack logic and the system interconnection mesh 215). For example, the protocol stack logic can be incorporated as Petition 870200023618, dated 03 / 23 / 2026, page 26 / 263 17 / 128 an agent or controller for a particular non-coherent load / store interconnection protocol (e.g., PCIe, CXL.io, etc.) and may include lower-level layer logic 305 (e.g., circuit-set deployment) including physical layer logic and link layer logic. Transaction layer logic 310 may also be provided and may be the layer that interfaces with the converter 315 via the SFI interface (e.g., 205a, 205b). Temporary stores 225 (e.g., 1 / 0 / queue (I0Q) temporary stores) may be provided and used to hide the physical link latency between the device and the host. The depth of such temporary stores 225 is typically shallow, and the number of logical write ports required is the number of concurrent packets available from the link in 1 clock cycle.For example, in one instance, for PCIe Gen5 speeds (32 GT / s), up to 4 packets can arrive in a 1 GHz cycle, so 4 logic gates would be needed in such an example in order to process these packets concurrently, given that these packets could potentially be of different flow control classes and / or virtual channels. Mesh-side temporary stores 230 (e.g., ProcQ temporary stores), on the other hand, can be deployed as deep temporary stores that are used to hide CPU mesh latencies (e.g., for input writes, which translates to request fetch latency). Petition 870260023612, dated 03 / 23 / 2026, page 23 / 263 18 / 128 data ownership and confirmation for coherence domain). These can be single or multiple write ports. In split-queue deployments, SFI semantics can also enable additional optimizations (e.g., on the ProcQ side to perform “batch processing” of transactions). In fact, SFI semantics are geared toward improving temporary storage deployments in a variety of system configurations, providing a balance of receiver complexity with bandwidth scaling capabilities, among other illustrative advantages.

[0040] Among the exemplary features adopted in an example, the enhanced SFI interface, receiver decoding can be simplified, with interface scaling to support a wide range of data payloads (e.g., from as small as 4B to as large as 4KB (or more)). An enhanced continuous transmission interface can allow multiple packets to be delivered in the same cycle, enabling a scalable interface across a variety of payload sizes while maintaining a common set of semantics and ordering (e.g., PCIe-based, etc.). Configurable parameters can include the number of logical write ports on the receiver (e.g., 1 or 2), which can be supported by defining rules for the interface restricting the number of different packets or headers transmitted in a clock cycle to the use of a corresponding number of flow control classes. Petition 870200023618, dated 03 / 23 / 2026, page 28 / 263 19 / 128 and / or virtual channels. Reducing the number of logical recording ports on the receiver can save significant complexity and area. Additionally, as noted above, an improved continuous transmission interface can allow header processing (e.g., of the header received through a dedicated header channel) on the receiver to begin while data is in continuous transmission to improve latency (e.g., in the case of CPU Host, to help overlap property request latency with an incoming data stream).

[0041] Compute Express Link, or CXL, is a high-bandwidth, low-latency packet or discrete link that supports dynamic protocol multiplexing (or muxing) of a coherence protocol (CXL.cache), a memory access protocol (CXL.mem), and an I / O protocol (CXL.io). CXL.cache is an agent-based coherence protocol that supports host memory device caching, CXL.mem is a memory access protocol that supports device-fixed memory, and CXL.io is a PCIe-based non-coherent I / O protocol with enhancements for accelerator support. CXL is thus intended to provide a rich set of protocols to support a wide spectrum of devices, such as accelerator devices. Depending on the particular accelerator usage model, all CXL protocols (CXL.io, CXL.mem, CXL.cache) or only a subset may be enabled to provide a high-bandwidth, low-latency path to a Petition 870260023612, dated 03 / 23 / 2026, page 20 / 264 20 / 128 corresponding computing device or block (e.g., an accelerator) for accessing the system.

[0042] As noted above, in some deployments, agents used to deploy a CXL.io protocol can couple to the system mesh using an SFI interface, as described in this document. For example, referring to Figure 4, a simplified block diagram 400 is shown illustrating exemplary CXL agents and the coupling of such agents to a mesh. Figure 4 shows an exemplary system topology for ports supporting a CXL link 415. For example, a CXL link 415 can couple the CPU host device 405 to another device 410 (e.g., a memory device or accelerator device). Each agent (on devices 405, 410) can include link layer logic (e.g., 420a-b, 425a-b) to support each of the CXL subprotocols (e.g., CXL.io, CXL.mem, CXL.cache). In the case of CXL.mem and CXL.cache, a common controller (e.g., 425a-b) can be used. For CXL.Alternatively, a 420a-b controller can be provided that is separate from the coherent CXL.mem and CXL.cache protocols. Protocol multiplexing can be facilitated through CXL arbitration / multiplexing logic (e.g., 425a-b, deployed in a hardware circuitry), which interfaces with a Flex Bus™ physical layer (e.g., 430a-b). The Flex Bus can be deployed as a flexible high-speed port that is statically configured to support either PCIe or CXL. Petition 870260023612, dated 03 / 23 / 2026, page 20 / 263 21 / 128 allows either the PCIe protocol or the CXL protocol to be sent over a high-bandwidth link outside the packet. Protocol selection on the Flex Bus PHY 430a-b can occur during the reinforcement time via auto-negotiation, as in the application.

[0043] Continuing with the example from Figure 4, a first type of 450a, 450b interface is used for coherent protocols such as CXL.cache and CXL.mem, while another different wire interface definition (e.g., 205', 205”) (e.g., an SFI interface) is used for payload / store protocols such as PCIe and CXL.io. In one example, SFI 205', 205” serves as an intermediate interface, which makes no assumptions about specific protocol or application responsibilities between the transmitter and receiver and provides a scalable continuous transmission interface that can meet the high bandwidth requirements of payload / store protocols (e.g., PCIe, CXL.io, etc.).The SFI does not contain a standalone protocol definition; the SFI semantics provided to support different protocols with the capability to be mapped to flow control and virtual channel semantics provided by the SFI definition, among other examples and other interface deployments.

[0044] As shown in Figure 4, a system can employ the exemplary interface 450a, 450b to allow wires to be shared in the fabric and achieve cable efficiency in the fabric and agent perimeters, allowing different coherent protocols. Petition 870260023612, dated 03 / 23 / 2026, page 28 / 263 22 / 128 share common wires. For example, the channels of various protocols originating from agents can be carefully mapped to a minimum set of physical and virtual channels, so that the bandwidth and channel isolation requirements of the agents and protocols are met with the lowest total wire count. The 450a, 450b interface can map these multiple protocols to a common set of channels and can use common virtualization and flow control features on these channels, among other exemplary deployments.

[0045] In some deployments, an enhanced continuous transmission interface may be deployed that is adapted to support a load / store protocol based at least in part on PCIe or PCIe semantics (e.g., PCIe or CXL.io). For example, a supported protocol may utilize packet formats based on formats defined by PCIe. Additionally, notions of Flow Control / Virtual Channel may be extended from PCIe definitions. It should be understood that other additional protocols (e.g., non-PCIe or non-CXL protocols) may also be supported by such SFI interfaces. In fact, although many of the examples discussed herein refer to deployments and protocols based on PCIe or CXL.io, it should be understood that the principles, features, and solutions discussed herein may be more generally applied, for example, to a variety of other protocols. Petition 870260023612, dated 03 / 23 / 2026, page 23 / 263 23 / 128 continuous loading / storage or transmission, among other illustrative systems.

[0046] In some deployments, an SEI interface may have separate Header (HDR) and Data channels or buses, each of which may carry headers or payloads from multiple packets concurrently. Furthermore, formalized rules may be defined and adopted in the agent logic to control how packets are packaged / unpacked on the header and data interfaces. For example, an additional metadata channel, or bus, may be provided on the enhanced interface to carry metadata to enable the receiver to identify how to unpack the headers / data sent on the header and payload data channels respectively. Through separate parallel header and data channels, a system (e.g., the root complex of a CPU host) may enjoy latency benefits, for example, potentially receiving multiple headers before the corresponding payload is received.This resulting delivery time can be used by the system to process headers and the start fetch property for cache lines for multiple header requests, while the data from these requests is still in continuous transmission. This helps to overlap latencies and reduces dwell time in temporary storage, among other illustrative advantages. Petition 870260023612, dated 03 / 23 / 2026, page 30 / 263 24 / 128

[0047] Referring to Figure 5, a simplified 500 block diagram is shown that illustrates an exemplary deployment of an SFI interface. For example, in each instance of an SFI interface, a set of physical lanes (e.g., wires or other conductors) may be provided assigned to various channels, which incorporate a logical set of signals defined for the interface and assigned to respective physical lanes of the interface. Each device may possess corresponding SFI pins and logic (deployed in a set of hardware and / or software circuits) to deploy its end (the transmitter or receiver), or instance, of the interface and couple to the physical lanes that incorporate the connection between the transmitter and receiver on the interface. An instance of an SFI interface may additionally define two channels for sending packets or other data transfer messages from the transmitter to the receiver.Specifically, in some deployments, the SFI 205 interface may include a Header Channel (HDR) that incorporates a set of signals (e.g., 505, 515, 520) which are, respectively, a first set of multiple interface lanes for use in sending header data for the packet. The SFI interface additionally includes a Data Channel (DATA) that incorporates another set of signals (e.g., 510, 525, 530) that are mapped to an additional set of multiple lanes of the 205 interface and are for use in sending payload data for the message. The HDR channel signals may include a primary HDR signal 505 to carry the header itself. Petition 870200023618, dated 03 / 23 / 2026, page 34 / 264 25 / 128 as a 515 header metadata signal, and a 520 header credit return signal (directed from the receiver to the transmitter). Similarly, the DATA channel may also include a main 510 DATA signal to carry the payload data, as well as a 525 data metadata signal, and a 530 data credit return signal (also directed from the receiver to the transmitter), among other exemplary signals. In some deployments, a SEI 205 interface may additionally include a global layer or channel (e.g., 550) that includes bidirectional control signals that apply across all physical channels (e.g., HDR and DATA) of the interface. For example, the global channel may carry a set of global control signals that can be used to perform interface initialization or shutdown, communicate controls or parameters to the interface, among other features.

[0048] Each of the HDR and DATA channels can carry multiple packets in the same transfer cycle. Since most load / store protocols rely on ordering semantics, SFI assumes implicit ordering when multiple packets are sent in the same cycle. Packets can be ordered, for example, from least significant position to most significant position. For example, if TLP 0 starts from byte 0 of header signal 505 and TLP 1 starts from byte 16 of header signal 505, then the receiver considers TLP 1 to be ordered behind TLP 0 when such rules of Petition 870260023612, dated 03 / 23 / 2026, page 32 / 263 26 / 128 ordering is applied. For transfers across different clock cycles, the ordering rules of the relevant protocol are followed (e.g., SFI carries all PCIe ordering rules when used for PCIe). In cases of link subdivision (e.g., splitting the overall link lanes into two or more narrower links (e.g., associated with their respective root ports)), the different ports from the controller's perspective map to different virtual channels in SFI. For example, in such cases, deployments may support multiple port configurations within the same physical block (e.g., deployed as an agent or controller). In these cases, the same physical SFI channel may be used to transfer packets to different ports, with each port mapped to its own set of virtual channels (e.g., 1 or more virtual channels per port), among other exemplary deployments.

[0049] A set of parameters can be defined for an instance of an SFI interface to configure aspects of the instance. For example, the metadata signals of the HDR and DATA channels can be based on one or more configurable parameters. For example, the parameters can identify how the metadata signals carry metadata to transmit information about the position of different packets within a single transfer, among other illustrative information. For example, in SFI, packet headers that have data associated with them send the packet header in the HDR channel and send the data. Petition 870200023618, dated 03 / 23 / 2026, page 36 / 263 27 / 128 are associated separately in the DATA channel. There may be no guarantee of timing relationship between DATA channel and HDR transfers. It is assumed that the receiver tracks the length of data associated with each received header and only processes the relevant data size. The data size may be sent with the packet header information (e.g., a PCIe deployment, using a PCIe packet header format, identifies the amount of data in the length field of the PCIe TLP header to indicate how many 4-byte portions of data are associated with that header).The information in the metadata sent through the metadata signals can also be used by the receiver to determine which headers map to which data (e.g., through combinations of virtual channel ID and flow control), parity information, header format information (e.g., header size), among other exemplary information.

[0050] A global signal layer or channel (e.g., 550) can carry signals that apply across all physical channels of the 205 interface, such as control signals, vendor-defined signals, and other signals that enable other exemplary functionality. For example, the global channel 550 can carry signals that are also used for interface initialization and shutdown (as in the examples discussed below). Table 1 describes an exemplary deployment of the signals of a global channel of an exemplary SFI interface. Petition 870260023612, dated 03 / 23 / 2026, page 33 / 263 28 / 128 TABLE 1: SIGNALS FROM THE GLOBAL LAYER Signal Class Signal Name Width Direction Description Initialization txcon_req 1 bit TxA Rx Transmitter connection request (0 to 1 connection request, 1 to 0 disconnect request) rxcon ack 1 bit RxATx Receiver connection confirmation (0 to 1 connection confirmation, 1 to 0 disconnect confirmation) rxdiscon nack 1 bit RxATx Receiver disconnection NACK rx_empty 1 bit RxATx Receiver queues are empty for all channels, and all credits have been returned. Vendor Defined Tx vendor field VT bits Tx A Rx Optional signal to send vendor-defined static / global information from TX to RX. Rx vendor field VR bits Rx A Tx Optional signal to send vendor-defined static / global information from RX to TX.

[0051] The HDR channel carries the header of the transmitter's request messages to the receiver. A variety of information can be encapsulated in the (protocol-specific) fields of a header transmitted using the HDR channel, including address and other protocol-level command information. Table 2 describes an exemplary deployment of the signals of an HDR channel from an exemplary SFI interface. TABLE 2: HDR LAYER FIELDS Signal Class Signal Name Width Description VALID hdr_valid M bits Indicates the start of a new packet at the corresponding header byte. There is a fixed association between the individual bits of hdr_valid and the header bytes. HDR Header H bytes Header information. May contain multiple packets transferred in the same cycle. FC and VC information is embedded in the header information. HDR_METADATA hdr_info_bytes 2*M bytes Indicates header size, flow control, virtual channel, and parity information. CREDIT hdr_crd_rtn_valid 1 bit Valid credit return hdr_crd_rtn_fc_id 4 bits Identifies the flow control class for this credit return hdr_crd_rtn_vc_id 4 bits Identifies the virtual channel for this credit return hdr_crd_rtn_value N bits Indicates how many credits are returned in this cycle Petition 870260023612, dated 03 / 23 / 2026, page 38 / 263 29 / 128

[0052] The header size can be a predetermined parameter based on the expected or required sustained peak bandwidth of the system. An SFI interface (and corresponding logic) can enforce rules for the HDR channel, such as having a packet header start and end in the same transfer cycle. Multiple packet headers can, however, be sent in the same cycle by sending one of the packet headers in a first subset of the header signal lanes and the other packet header in another subset of the header signal lanes. The interface can, however, define that the first packet in a valid header transfer starts in the header signal lanes corresponding to byte 0 of the header field (logically represented by the header signal lanes).

[0053] Valid header signals (hdr_valid) can be asserted to indicate corresponding valid values ​​in the header signal lanes. In some deployments, the number of header signal lanes can be logically divided into byte subsets (e.g., 16-byte or 32-byte lane width in each subset) corresponding to the size of one of the protocol headers to be carried in the header signal. Furthermore, each valid header lane can be mapped to one of the subsets to indicate that valid header data is being sent in a corresponding subset among the header signal lane subsets. Additionally, the header metadata signal Petition 870260023612, dated 03 / 23 / 2026, p. 39 / 263 30 / 128 (hdr info bytes) can carry metadata (e.g., aligned with one of the headers carried in the header signal) to describe key attributes that can be used by the receiver to decode the corresponding header.

[0054] A physical DATA channel of an SFI interface can be used to carry payload data for all requests that have associated data. In SFI, there may be no explicit timing requirement or relationship between the HDR channel and associated data carried on the DATA channel. However, transmitters may be equipped with logic to check HDR channel and DATA channel credits before scheduling either header data on the HDR channel or payload data on the DATA channel. Table 3 describes an exemplary deployment of the signals from a DATA channel of an exemplary SFI interface. Petition 870260023612, dated 03 / 23 / 2026, p. 40 / 263 31 / 128 TABLE 3: DATA CHANNEL FIELDS Signal Class Signal Name Width Description VALID data_valid 1 bit Indicates the start of a new packet in the corresponding header byte. It has a fixed association between the individual bits of hdr_valid and the header bytes. DATA data D bytes Header information. Contains multiple packets transferred in the same cycle. FC and VC information is embedded in the header information. DATA_METADATA data_start DS bits Indicates the start of a new data packet in the corresponding data byte. They have a fixed association between the individual bits of data_start and the data bytes. The DS parameter is determined by the maximum number of separate packets that need to be sustained per cycle. data_info_byte DS*8 bits For each data_start bit, there is a data_info_byte, which indicates the FC ID and VC ID of the associated data packet. data_end DE bits Indicates the end of a new data packet in the corresponding 4-byte data portion.It has a fixed association between the individual bits of data_end and the data bytes. The DE parameter is determined by the total data width D divided by the size of a defined data portion (e.g., a 4-byte portion), since any of the quantized data portions can be the last data portion. data_poison DE bits Indicates that one or more bytes of the associated data packet are contaminated. Rx treats the entire payload as contaminated. data_ecrc DE bits If error correction code is supported, it is asserted when the corresponding bit of data_end is asserted and indicates that the last data portion carries the error correction code (e.g., end-to-end cyclic redundancy check (ECRC) code).CREDIT data_crd_rtn_valid 1 bit Valid credit return data_crd_rtn_fc_id 4 bits Identifies the flow control class for this credit return data_crd_rtn_vc_id 4 bits Identifies the virtual channel for this credit return data_crd_rtn_value N bits Indicates how many credits are returned in this cycle.

[0055] In SFI interface deployments, payload data can be sent on the DATA channel data signal according to a granularity of Petition 870260023612, dated 03 / 23 / 2026, page 48 / 263 32 / 128 multiple bytes (e.g., 4-byte granularity). Consequently, the data for any payload can be identified as terminating in a particular data “portion” (e.g., a particular 4-byte portion). As an example, if the width of the data signal D is 64 bytes, the number of potential data end positions is DE = 64 / 4 = 16, with data end[0] corresponding to data bytes[3:0], data end[l] corresponding to data bytes[7:4], data end[DE-l] to data bytes[Dl:D-4], and so on. The data start can use the same or different granularity relative to the end in the data signal. An instance of an SEI interface can be parameterized to support (and limit the number of payload starts accordingly) a maximum number of DS starts in a clock cycle.As an example, if the width of the data signal bus D is 64 bytes and the SFI interface instance is configured to limit the number of starts in a cycle to 2, DS = 2, effectively splitting the data bus into two 32-byte portions in which a new payload can begin to be sent. For example, in an instance where D = 62 and DS = 2, data_start[0] could correspond to a data portion starting at data byte [0] and data_start[1] corresponding to a data portion starting at data byte

[32] , among other examples (including examples with finer or finer granularity at the start of the data and at the end of the data portions (e.g., DS>2), smaller or larger data bus sizes, etc.). Petition 870260023612, dated 03 / 23 / 2026, p. 42 / 263 33 / 128

[0056] In an exemplary deployment of a DATA channel of an SEI interface, the width of the data start signal can be equal to DS and the signal can effectively act as a mask to identify each corresponding portion of data in the data signal (e.g., aligned on the same clock cycle) that corresponds to the start of a respective payload. Furthermore, each data start bit can have an associated data info byte signal sent with it that indicates metadata for the corresponding payload. In some deployments, data_info_byte is sent only once for a given payload (e.g., with the corresponding data start portion and data_start_bit), while in other cases, metadata can be sent (e.g., repeatedly) to correspond to each portion of data in the same payload, among other exemplary deployments.In a deployment, the data_info_byte signal can indicate the respective FC ID and VC ID of the corresponding packet (for example, with 4 bits (e.g., data_info_byte[3:0]) carrying the FC ID and another 4 bits (e.g., data_info_byte[7:4]) carrying the VC ID), among other illustrative information for use by the receiver in processing the data payloads sent through the data signal bus.

[0057] Unlike the HDR channel, in some deployments of a DATA channel, portions of data from the same packet can be transferred across multiple cycles. For example, the raw data bus width could be deployed as 64B per cycle, Petition 870260023612, dated 03 / 23 / 2026, p. 40 / 264 34 / 128 allowing a 128B data packet to be transferred across 2 clock cycles. In some deployments, once a payload has started transmitting, the transmitter can ensure that all relevant data portions in the payload are transferred consecutively from LSB to MSB and across successive clocks (e.g., without any gaps or bubbles). In some deployments, only one packet of a particular FC ID / VC ID combination can be sent on the interface at a time (with the FC ID / VC ID combination only reused after the preceding packet using the combination finishes sending). In some deployments, packets with different FC ID / VC ID combinations can be interleaved on an SFI interface (e.g., with a packet of one FC ID / VC ID combination being interrupted to send at least a portion of a packet with another FC ID / VC ID combination), among other examples.

[0058] The granularity of credits in the data channel can also be configurable (e.g., at project compile time) and can correspond to a plurality of N-bytes. For example, in one example, the granularity may need to be a multiple of 4 bytes. If the credit granularity is chosen to be 16 bytes, then even a 4-byte data packet transferred uses a 16-byte credit value, among other exemplary deployments.

[0059] Figure 6 is a simplified block diagram 600 that illustrates an exemplary deployment of a Petition 870260023612, dated 03 / 23 / 2026, p. 41 / 263 35 / 128 Temporary receiver storage for use with an exemplary SFI interface. In one example, the temporary receiver storage can be deployed as a linked list with a single write port and shared between two virtual channels (e.g., VCO and VC1) of class 1 flow control (ECO). In this example, four headers per cycle can be received on the corresponding SFI interface. The linked list is managed in blocks (e.g., 630a-c) of four header locations at a time. Although the linked list may appear to be logically in contiguous memory, physically the blocks may be deployed non-contiguously or even on separate storage elements. In one example, all locations within a given block (e.g., 630a) must be populated before moving on to the next block (e.g., 630b).Temporary storage is allocated by the receiver one block at a time, therefore corresponding shared credits can also be at a block granularity. In deployments where a set of 4 headers (e.g., 605a-d) in a block (e.g., 630a) is realized to consist of separate storage structures, each of these storage columns can be successfully deployed with only a single write port. For example, each of the columns represented in the linked list temporary storage of Figure 6 can be physically deployed as a temporary storage / element to distinct storage with a respective single write portion. Furthermore, relief. Petition 870260023612, dated 03 / 23 / 2026, page 42 / 263 36 / 128 timing and segmentation potentials can be unlocked using "block" management of linked list indicators (e.g., 615, 620, 625), since the next block indicator only needs to be fetched once in 4 headers (in the example in Figure 6). In some continuous transmission protocols, the receiver cannot assume that there is only one FC / VC combination per cycle in the general case and therefore may be designed and equipped with multiple recording ports (e.g., since FC / VC tails may collide within the same storage column).

[0060] As discussed above, an SFI interface (and the corresponding logic and temporary storage / trackers used by the transmitter and / or receiver to deploy their half of the interface) can enable the segmentation of header processing while data is in continuous transmission. In fact, the latency savings achieved by the entire system, in terms of header processing, translate directly into temporary storage savings at the receiver. In the context of load / store protocols, it is assumed that a receiver will separate the header and data internally anyway, since headers are heavily consumed by the control path, while data is mostly isolated to the data path. By splitting the header and data channels in an exemplary SFI interface, the headers of the latest requests can even divert data from previous requests, and this can allow the Petition 870260023612, dated 03 / 23 / 2026, page 46 / 264 37 / 128 The receiver initiates header processing while the data transfer is being completed. In the context of a host CPU processing incoming writes (device to host), this can translate into an advantage in obtaining ownership of the relevant cache lines, among other exemplary use cases and advantages. In fact, since ownership seeking is one of the most significant drivers of latency when processing writes, overlapping it during continuous data transmissions can help reduce overall latency and temporary CPU storage. No locking is avoided by ensuring that the transmitter checks both header and data credits before sending header or data.

[0061] In some deployments, each VC and FC defined for an SFI interface must use one credit to send any message and collect credit returns from the receiver. The source can consume the entire credits required for a message to complete. Transmitters check both HDR channel and DATA channel credits before sending corresponding messages on the respective channel to the receiver. The granularity of HDR and DATA channel credits is predetermined between the TX and RX. For example, the granularity of credits on the data channel can be configured (e.g., at project compile time) to be only a plurality of N-bytes. For example, in one instance, the granularity might need to be a multiple of 4 bytes. If the credit granularity is chosen to be 16 bytes, then even a Petition 870260023612, dated 03 / 23 / 2026, page 44 / 264 38 / 128 4-byte data packets transferred use a 16-byte credit value, among other exemplary deployments. In one example, FC IDs can be based on PCIe semantics (e.g., 4'hO = Posted, 4'hl = Not Posted, 4'h2 = Completions), among other exemplary deployments. Furthermore, each of the physical channels (e.g., DATA and HDR) can be equipped with dedicated credit return wires (which, unlike the remaining channels, flow from the receiver to the transmitter). For example, during operation, the receiver returns credits whenever it has processed the message (or secured a temporary storage position for the next transaction).

[0062] In some deployments, SFI allows two schemes to support sharing of temporary stores between different FC and VC IDs. In both schemes, the receiver must advertise the minimum number of dedicated resources needed for forward progress assurance. For large packet transfers, this means the maximum payload size is based on the dedicated credit advertisement. If shared credits are used, the transmitter and receiver must predetermine which credit type, or scheme, should be used. This determination can be made at design time in some deployments. In alternative deployments, the credit scheme can be determined dynamically (e.g., based on parameters written to corresponding configuration registers), among other examples. Petition 870200023618, dated 03 / 23 / 2026, page 48 / 263 39 / 128

[0063] One of the two schemes for credit sharing can be managed by the transmitter. In this scheme, the transmitter is responsible for managing shared temporary stores at the receiver. One or more shared credit pools are advertised or consumed with spare VC ID / FC ID encodings. When the transmitter consumes the shared credit pool credit, it sends the packet using the corresponding VC ID / FC ID encoding. When the receiver deallocates a transaction that used the shared credit, it performs a credit return in the corresponding VC ID / FC ID combination. In some deployments, a bit may be provided in the header (along with a corresponding signal in the HDR channel) to indicate whether the credit is a shared credit or not.Consequently, the receiver may have to additionally decode the header packet to explicitly determine the packet's actual VC ID or FC ID, among other examples.

[0064] In an exemplary transmitter-managed credit sharing deployment, the exemplary shared credit pooling mapping advertised by the receiver (e.g., in a PCIe-based deployment) can support two VCs on the link and adopt the following exemplary mapping shown in Table 4: Petition 870260023612, dated 03 / 23 / 2026, page 49 / 264 40 / 128 TABLE 4: EXEMPLARY CODING FOR SHARED CREDITS Encoding Description VC encoding 4'bO Maps to VCO advertised by PCIe on the link VC encoding 4'b1 Maps to VC1 advertised by PCIe on the link FC encoding 4'bO Posted (P) FC encoding 4'b1 Not Posted (NP) FC encoding 4'b2 Completions (C) VC encoding 4'b2; FC encoding 4'bO Shared credit pooling 1, all VCs, classes P or C can use these shared credits VC encoding 4'b2; FC encoding 4'b1 Shared credit pooling 2, all VCs, NP can use these shared credits

[0065] The other of the two credit sharing schemes can be receiver-managed. In a receiver-managed scheme, the receiver is responsible for managing shared temporary stores. Only dedicated credits are advertised to the transmitter. Typically, the advertised dedicated credits cover the point-to-point credit circuit through the SFI, and shared credits are used to cover the larger credit circuits (e.g., the CPU mesh or Application Layer latencies). After a transaction with a particular FC / VC ID is received, and shared credits are available, a credit can be returned for that FC / VC ID combination (e.g., without waiting for the transaction to deallocate from the receiver queue). This implicitly generates a shared temporary storage point for that FC / VC ID.Internally, the receiver tracks the credits returned to the transmitter on an FC / VC basis and additionally tracks the credits currently consumed by the transmitter. Petition 870260023612, dated 03 / 23 / 2026, page 36 / 263 41 / 128 this tracking, the receiver can guarantee the maximum number of temporary storages used by FC / VC. The receiver can guarantee the dedicated resources needed to ensure progress forward, among other exemplary deployments.

[0066] Error handling for illegal flow control cases can result in undefined behavior. Consequently, the SFI interface logic in the agents and mesh can check for illegal cases to trigger assertions in RTL and also fatal register / signal errors to allow post-silicon debugging. For example, SFI can maintain consistency between HDR and DATA streams, meaning that the transmitter should send data payloads in the same order as it is sending the corresponding headers and vice versa. In some deployments, the receiver logic may include functionality to detect and flag fatal errors for violations, among other exemplary error handling features. In some deployments, SFI provisions for data placement should be sent at the end of a data transfer.In the case of occasional errors, the property request could be discarded / rewritten without modification, or the host could choose to contaminate the relevant cache lines and write the updated data, among other examples.

[0067] Returning to Figure 7, a representation of an exemplary 700 metadata format that can be carried in the header metadata signal lanes is shown. The last bytes and bits Petition 870260023612, dated 03 / 23 / 2026, page 38 / 263 42 / 128 significant bits are shown on the right. P (705) is the parity bit for a matching header. In some deployments, support for the parity bit may be optional (e.g., and the 705 parity bit treated as an additional reserved bit). When supported, parity can be achieved, for example, by performing XOR on the last bits of a header packet. In some deployments, both the 700 bits and the non-parity bits of the associated metadata may be XORed to determine parity, among other examples. The 0 bit D (710) indicates whether the header has matching payload data associated with it. All reserved bits (e.g., 715) may be ignored by the receiver or may need to be driven to 0 by the transmitter. In some deployments, mesh switches / routers may be required to propagate the 715 reserved bits as is, without any modification.In some deployments, the reserved bits 715 may be used for vendor-defined encodings or future information, among other examples. The header size (HDR size) 725 in the example metadata 700 may specify the header size (e.g., in 4-byte granularity). When computing the header size, the length of the header metadata (700) may be ignored (and not considered part of the header).

[0068] In SFI interface deployments, several maximum packet headers that can be transmitted in 1 cycle on the interface can be predetermined (for example, and registered in a configurable parameter of the Petition 870260023612, dated 03 / 23 / 2026, page 32 / 263 43 / 128 interface). The maximum packet headers per cycle can be determined by the width (or number of lanes) (H) of the header signal and the maximum packet header size. An SFI interface can be deployed (and designed) so that the header width (H) allows the use of common wrapper to sustain maximum throughput. As an example, assuming that a common wrapper application header size is 16 bytes (e.g., mapping to 4 DWord headers on PCIe), and that the interface should sustain 2 headers per cycle, H = 2 * (16) = 32 bytes. A corresponding valid signal (and lane) can be included in the HDR channel to match the desired number of headers per cycle.As an example, if it is desired that the interface support up to 2 headers per cycle, a corresponding number M=2 of valid lanes can be defined to support a valid signal for each of the 2 potential headers in a cycle (for example, with hdr_valid[O] corresponding to a header that starts at byte 0 of the header signal, and hdr_valid[l] corresponding to a header that starts at byte 16 of the header signal). In some cases, one or more of the header formats of a supported protocol may be too large to be sent in only one of the subsets of lanes defined in the header signal (and assigned to a respective valid signal lane), meaning that such headers may use two or more subsets of lanes in the header signal for transmissions (and only one first (last significant bit) of the two or more signals). Petition 870260023612, dated 03 / 23 / 2026, p. 50 / 263 44 / 128 valid associated headers can be asserted). In such cases, when the maximum headers per cycle are set to 2, if a larger header format must be sent in the header signal, only 1 header can be transferred in that cycle and hdr valid[l] is not asserted, among other examples.

[0069] Continuing with the example from Figure 7, header metadata may additionally include information for use in flow control for the header (and related packet). For example, the metadata may include a virtual channel (VC) identifier (ID) 720 for the header and a flow control class (FC) ID 730 for the header. In some cases, packet ordering may be based on the VC ID and FC ID (e.g., the combination of the VC ID and FC ID) of the packet. In some deployments, the parameters of an SFI interface may be configured to define, for the interface, a predetermined number of maximum FC and VC ID combinations that may be allowed for use in any given transfer cycle (e.g., clock cycle) of the interface.This maximum number of FC-VC combinations can be advertised or otherwise defined in both transmitter and receiver interface logic (e.g., at project compile time). This maximum value can be set, for example, to help minimize write ports on receiver storage when temporary receiver storage is shared between supported FCs and / or Ves. As an example, an interface could be... Petition 870200023618, dated 03 / 23 / 2026, page 54 / 264 45 / 128 parameterized to accept a maximum of two different FC-VC combinations in a cycle, so that in any given cycle all packet headers transferred between belong to at most two different FCs within the same VC, from the same FC but to two different VCs, or from the same FC-VC combination.

[0070] Transmitters can use credits associated with FCs, VCs, or FC-VC combinations to determine whether a packet can be sent over the channel. For example, if a packet header has associated data, the packet header is sent on the HDR channel and the associated data is sent on the DATA channel. Before sending header data or payload, the transmitter can check (e.g., a tracking log in local memory) for available credits for both header and payload data (and the corresponding HDR and DATA channel) before scheduling the header or payload data transfer. In some deployments, the credit granularity for the header channel can be set to the maximum supported header size. For example, if the maximum supported header size is 20 bytes, then 1 credit on the header channel might correspond to 20 bytes of storage at the receiver.In some examples, even if only a 16-byte header needs to be sent, 1 full credit is consumed, corresponding to the full 20 bytes, among other examples and alternative flow control and crediting implementations. Petition 870260023612, dated 03 / 23 / 2026, page 52 / 263 46 / 128

[0071] Referring to Figure 8, a simplified timing diagram 800 is shown to illustrate an example of header transfer using an exemplary SFI interface header channel. The header channel may include a clock lane, one or more dedicated lanes for valid header signals (e.g., 810, 825), dedicated lanes for communicating header metadata (e.g., 815, 830), and dedicated lanes for deploying multiple bytes of a header bus (e.g., 820, 835). In the example in Figure 8, multiple valid signals are provided to govern the sending of valid header data in corresponding subsections of the header bus.For example, header lane 810 can carry valid signals corresponding to lanes (e.g., 820) that deploy bytes 0 to 15 of the header bus, and header lane 825 can carry valid signals corresponding to lanes (e.g., 835) that deploy bytes 16 to 31 of the header bus. Correspondingly, valid signal 810 can be asserted as long as valid data is sent on bytes 0 to 15 of the header bus (e.g., as in clock cycles 1, 2, and 4), and similarly, valid signal 825 can be asserted to correspond to valid data sent on bytes 16 to 31. In one example, as in Figure 8, the corresponding header data can be sent in alignment (e.g., the same clock cycle) as the corresponding asserted valid signal, whereas in alternative deployments, a delay can be set. Petition 870200023618, dated 03 / 23 / 2026, p. 561611 47 / 128 between the assertion of a valid signal and the sending of header data, among other exemplary resources and deployments.

[0072] Continuing with the example from Figure 8, the subsections of lanes that deploy the header bus can also be associated with respective header metadata signals (or info hdr) (e.g., 815, 830). For example, header bytes 0 to 15 (e.g., 820) can be associated with a first header metadata signal 815, and header bytes 16 to 31 can be associated with a second header metadata signal 830. The header metadata signal can carry data (e.g., 8 bytes) per cycle that describes header attributes carried on the corresponding header bus lanes. In some cases, both subsections of the header bus can be used to carry a larger header, resulting in less than the maximum number of headers-per-cycle that is transmitted in a given cycle (e.g., clock cycle 4).When two or more subsections of the header bus are used to transmit a single header, in some deployments, only one of the corresponding metadata signals (for example, the signal corresponding to the least significant bytes of the header) can carry data, while the remaining metadata signals do not carry any metadata. In this way, a receiver can identify that more than one subset of header bus lanes is used to transmit a single header. Petition 870260023612, dated 03 / 23 / 2026, page 53 / 263 48 / 128 among other examples (for example, the assertion of one or both valid signals (e.g., 810, 825) corresponding to the header bus subsections used to communicate the header).

[0073] In the simplified particular example of Figure 8, the headers of five transaction layer packets (TLPs) are shown being transmitted over an exemplary SFI header channel. For example, header bus subsections 820, 835 may each carry headers of two distinct TLPs in clock cycles 1 and 2 (e.g., the TLP0 (840) and TLP1 (845) headers are in cycle 1, and the TLP2 (850) and TLP3 (855) headers are in cycle 2). This may be possible based on the header sizes of these respective packets. Furthermore, the corresponding header metadata (e.g., 865, 870, 875, 880) can be transmitted in the header metadata signals 815, 830 in cycles 1 and 2. The valid signals 810, 825 can be de-asserted in cycle 3 without causing the additional header data to be transmitted during that cycle.

[0074] In cycle 4, the header of another TLP, TLP4, must be transmitted. In this example, the size of the TLP4 header requires transport over both 820 and 835 header bus subsections in order to communicate the header over the HDR channel in a single clock cycle. For example, the headers (e.g., 840, 845, 850, 855) of TLPs 0 to 3 may have had a size of HDR SIZE=4, whereas the TLP4 header size is HDR SIZE=5. Correspondingly, Petition 870260023612, dated 03 / 23 / 2026, page 55 / 263 49 / 128 In this example, the TLP4 header bytes (860a-b) are transmitted on the lanes of both the 820 and 835 header bus subsections. In this example, only the valid signal 810 corresponding to the header bus subsection (or bytes) that carries the beginning of the header (or least significant bytes) is asserted high (at 890), while the other valid signal 825 remains unasserted in clock cycle 4. Similarly, only one of the header metadata signals (e.g., 815) can be used to carry the metadata information for the TLP4 header, with the metadata signal (e.g., 830) corresponding to the most significant bytes of the header carrying a null signal or other signal. In one example, TLP4 headers may conform to a PCIe-based protocol. In such instances, the TLP Hdr bytes follow the format described in the PCI Express Base Specification.In this example, hdr_start[0] is associated with header byte[0] and hdr_start[l] is always associated with a header byte

[16] , among other example implementations.

[0075] In some deployments, an SFI interface can be deployed as a synchronous interface, where both sides of the interface run on the same clock. However, transmitters and receivers may not need to coordinate resets on each respective device. Preferably, in some deployments, a defined initialization flow for the interface can define a separate handshake to ensure that the transmitter and receiver exchange information about the Petition 870260023612, dated 03 / 23 / 2026, page 59 / 263 50 / 128 reset and flow control before traffic begins on the interface.

[0076] Referring to Figure 9, a simplified timing diagram 900 is shown to illustrate an example of data transfer using a data channel of an exemplary SFI interface. In this example, the DATA channel includes a clock 905, a single valid signal 910 (e.g., on a single lane of the channel) and sets of lanes (e.g., 915, 920) that deploy one or multiple subsections of the data bus. In the particular illustrative example of Figure 9, subsections Xl are illustrated. When the valid signal 910 is asserted (for example, at 945), the data appearing on the data bus (and supporting signals (for example, 925, 930, 935, 940)) is considered valid. When the valid signal 910 is deasserted (for example, at 966), data transmission on the data bus must pause or stop until the valid signal is reasserted.

[0077] In some deployments of an SFI DATA channel, a data start signal may be provided, which is deployed in a set of lanes to deploy a corresponding number of bits of the data start signal. For example, the data start signal may be deployed as a bit vector with a corresponding data start lane (e.g., 925, 926, 928, etc.) that is mapped to a respective byte or byte range on the data bus. For example, each data start lane (e.g., 925, 926, 928, etc.) may be mapped to a corresponding subsection. Petition 870260023612, dated 03 / 23 / 2026, pp. 60 / 263 51 / 128 of the X+1 subsections of the data bus. For example, in an example where there are 8 subsections of the data bus, the start of the data signal may be composed of 8 bits or streaks, with each bit mapped to one of the subsections. When a first byte (e.g., as measured from the least significant byte to the most significant byte) of a payload is communicated in a particular clock cycle, the corresponding start of the data signal (e.g., 925) can be asserted (e.g., at 954) to identify the subsection (or fragment) of the data bus in which that first byte of payload can be found. With this, a receiver can identify a boundary between two payloads communicated on the channel.

[0078] As in the example of an HDR channel, an SFI DATA channel can also carry metadata in dedicated metadata signal lanes (data_info) (e.g., 930, 935) to describe corresponding payload data sent on the data bus. In some deployments, metadata for a payload may be communicated on the DATA channel in association with the start of that payload (e.g., aligned to the first byte of the payload and the corresponding data start signal). In fact, multiple metadata signals can be defined and carried on the DATA channel, one corresponding to each of the various corresponding subsections of the data bus (e.g., 915, 920). The subsections or fragments, in some deployments, may correspond to the same logical fragments used in the data start signal (and / or the signal). Petition 870260023612, dated 03 / 23 / 2026, pp. 68 / 263 52 / 128 of data end 940). For example, when a particular fragment carries the first bytes of a new payload, a corresponding signal of the metadata signals (e.g., 930, 935) is responsible for carrying the metadata for that payload. As an example, as shown in Figure 9, in clock cycle 1, the start of the TLPO payload (950) might begin on a first subsection (e.g., 915) of the data bus. Correspondingly, the data start signal 925 might indicate (on 954) that the subsection (e.g., corresponding to Byte 0 of the data bus) carries the start of a new payload. Other subsections (e.g., 920) of the data bus might be used to communicate further other fragments (e.g., 952) of the same payload.Additionally, one of the metadata signals (e.g., 930) corresponding to the first subsection (e.g., 915) of the data bus can be encoded with the metadata (e.g., 956) for the TLPO payload.

[0079] Continuing with the example from Figure 9, the payload data (e.g., 950, 952, 960) of TLPO can continue to be sent in multiple clock cycles on the data bus until all have been sent. The data end signal 940 can operate similarly to the data start signal with multiple lanes (e.g., 940, 942) mapped to identify a subsection of the data bus where a final fragment of payload data was sent within a corresponding clock cycle. A Petition 870260023612, dated 03 / 23 / 2026, pp. 62 / 263 53 / 128 The granularity of the subsections or fragments denoted by the data end signal can be greater, less than, or equal to that used in the data start and metadata signals. In one example, the subsections or fragments indicated by the data end signal 940 can be 4 bytes, among other examples. In the particular illustrative example in Figure 9, the final bytes / bits of the TLPO payload must be sent in a subsection “N” of the data bus bytes and lanes, as measured according to the granularity configured for the data end signal. Consequently, the lane (e.g., 940) of the data end signal mapped to subsection N can be asserted to identify that subsection N carries the end of the payload. In some deployments, the granularity of the subsections and portions of the data bus used by the data start, data end, and metadata signals can be configured through the corresponding parameter set for the SFI interface, among other examples.

[0080] Continuing with the example from Figure 9, a second payload of a second packet (e.g., TLP1) can be sent on the data bus (e.g., the start of the second packet being sent in a data portion / subsection “Y”). In some deployments, payloads from multiple packets can be sent concurrently on the data bus (e.g., using respective subsections of the data bus). In this example, the TLP1 payload ends, and the TLP1 payload begins on clock cycle 2. Correspondingly, both an end-of-data signal (e.g., 970) and a start-of-data signal (e.g., 970) are sent on clock cycle 2. Petition 870260023612, dated 03 / 23 / 2026, pp. 60 / 263 54 / 128 example, 964) are sent in the same cycle, where the start data signal 964 indicates the subsection or portion (for example, subsection “Y”, where 0 <Y<X) do barramento de dados no qual o início da carga útil aparece. No exemplo da Figura 9, o início do sinal de dados pode estar em uma granular idade de 1 byte e especificamente identificar o byte no barramento de dados em gue a carga útil começa (por exemplo, Byte 0 para a carga útil de TLPO, Byte Y para a carga útil de TLP1 etc.) . De modo correspondente, a largura do início de dados e sinais de fim de dados podem se basear na granularidade respectiva. Além disso, no exemplo da Figura 9, a carga útil de TLP1 começa a ser enviada no ciclo de relógio 2, porém a transmissão pode ser interrompida temporariamente através da desasserção do sinal válido 910 (em 966), com os bytes restantes (por exemplo, 972, 974) enviados quando o válido 910 é reassertado.In other examples, it may be necessary for the valid assertion to remain until all bytes of a payload in transit have been sent, among other exemplary deployments. It should be noted that the examples in Figures 8 and 9 are simplified; non-limiting examples are provided to illustrate more general principles (and alternative deployments) that can be implemented in the exemplary SFI HDR and DATA channels, among other examples.

[0081] In some deployments, a state machine or other logic may be provided on agent and fabric devices to participate in defined connection and disconnection flows for an SFI interface. By Petition 870200023618, dated 03 / 23 / 2026, page 64 / 264 55 / 128 For example, such flows can be invoked during escalation / reset when entering a low-power mode, among other exemplary states or events. In some deployments, SFI defines an initialization phase in which information about credit availability at the receiver (RX) is communicated to the transmitter (TX) after a connection is established. In other examples, the reset can be independently disengaged between the agent and fabric sides of the SFI. For independent reset, initialization signals can be conducted (e.g., on the global channel) to the disconnected condition when resetting, and no traffic can be sent until the initialization reaches the connected state. The disconnection flow can be further sustained by agents, for example, to reconfigure credits and conserve power.Without this flow, all SFI credits may be set to a final value before the first connection can proceed.

[0082] During initializations, the transmitter-receiver sides (e.g., the agent and fabric sides) of an SFI interface may exit reset at nearly or simultaneously. One end of the interface (e.g., after exiting reset) may have no implicit requirements for when the other end should exit reset. In some deployments, SFI may define an explicit handshake during initialization between the agent and the fabric to ensure that both endpoints (and all pipeline stages between them) are out of reset before any credits Petition 870260023612, dated 03 / 23 / 2026, pp. 62 / 263 56 / 128 or transactions are sent on the UFI interface. Correspondingly, after the reset, the receiver can start sending credits to be used by the transmitter.

[0083] Figure 10 is a diagram 1000 that illustrates an example state machine for initialization states in an exemplary deployment of the SFI interface. The states can include a Disconnected state 1010 (which can be entered based on a reset 1005), a Connecting state 1015, a Connected state (1020, 1035), a Disconnecting state 1025, and a Deny state 1030. Combinations of values ​​of the txcon_req signal, rxcon_ack signal, and rxdiscon_nack signals can indicate a respective initialization state. As an example, in the Disconnecting state 1025, the txcon_req signal can be LOW, the rxcon_ack signal can be HIGH, and the rxdiscon_nack signal can be LOW. Changing a particular value among the signal values ​​can cause a transition from one initialization state to another.For example, the Disconnecting state 1025, which changes the rxcon ack signal from HIGH to LOW, can cause a transition to the Disconnected state 1010, while changing the rxdiscon ack signal from LOW to HIGH can cause a transition to the NEGATE state 1030, among other examples, as illustrated in the example state machine in Figure 10. In a UFI interface, the respective initialization states are used to determine actions to be performed by the receiver and transmitter, such as the example actions described in Table 5 below. Petition 870200023618, dated 03 / 23 / 2026, page 66 / 263 57 / 128 TABLE 5: INITIALIZATION STATE ACTIONS txcon_req rxcon ack rxdiscon_nack Status Tx Actions Rx Actions 1 0 0 Connection Request (Connecting) Dissipate Credits NO Send Packets 1 1 0 / 1 Connected Dissipate Credits Send Packets Send Credits Dissipate Packets 0 1 0 Disconnection Request (Disconnecting) Dissipate Credits NO Send Packets 0 1 1 Deny (Disconnection Rejected) and need to return to connected state 0 0 0 Disconnected Release Credits NO Send Packets NO Send Credits NO Dissipate Packets 1 / 0 0 1 Illegal States n / an / a

[0084] Signaling rules can be defined for a set of global initialization signals. In one example, the txcon req signal can be defined so that a transition from 0 to 1 reflects a connection request and a transition from 1 to 0 reflects a disconnection request. Credit return signals can be provided, for example, with a valid credit signal (crd valid) and a shared credit signal (crd shared). In one example, crd valid = 1 can be defined so that it means it is releasing dedicated message credits for a protocol ID and a virtual channel ID, while crd_shared = 1 means it is releasing a shared credit (which can happen in parallel with a dedicated credit return message). In some deployments, a credit return behaves the same way during the first credit initialization as during Petition 870260023612, dated 03 / 23 / 2026, page 63 / 263 58 / 128 return of credit execution time. A 0 rx empty signal indicates all channel credits returned from the receiver and all receiver queues are empty (although this may not be related to messages being transmitted or in intermediate stores such as clock crossing queues, among other exemplary issues). In some deployments, a transmitter may check rx empty before initiating a disconnect. Through checking, this increases the probability of the disconnect being quickly accepted (e.g., in the absence of possible requests in transmission that have not yet been registered at the receiver). In some deployments, in order to further increase the probability of disconnect acceptance, the transmitter may deploy a timer delay after the last valid message sent so that the receiver pipeline has time to drain the receiver queues, among other exemplary features.In some deployments, during initialization, the transmitter sends messages as soon as any credits are available and does not depend on an assertion of rx_empty. Alternatively, a transmitter can stop sending any packets after initialization until rx_empty is asserted; the transmitter can use the received credits with an indication of the credits such that a receiver has announced. In an exemplary deployment of an SFI interface, a transmitter can send packets when it receives sufficient credits from the receiver. The transmitter can identify what the packet should be. Petition 870200023618, dated 03 / 23 / 2026, page 68 / 263 59 / 128 transmitted and determine that there are respectively sufficient HDR and Data credits for the package before transmission begins.

[0085] As further examples of signaling rules that can be defined in a UFI deployment, connection ACKs can be defined so that they always follow connection requests. As verified above, a connection request can be signaled by a txcon req transition from 0 1. This transition serves as an indication that the Tx transmitter is ready to receive credits and is in normal operation. An ACK can be signaled by an rxcon_ack transition from 0 to 1. An ACK can be held for an arbitrary period until a receiver is ready to complete. Similarly, disconnect ACKs or NACKs can be set to follow disconnect requests. A disconnect request can be signaled by a txcon_req transition from 1 to 0. A disconnect ACK can be signaled by an rxcon_ack transition from 1 to 1. 0. A disconnection NACK can be signaled by an rxdiscon_nack transition from 0. 1. A rule can be defined to require a receiver to either respond with an ACK or NACK for each disconnection request it receives, among other exemplary policies and deployments.

[0086] Returning to Figure 11, an example 1100 timing diagram is illustrated for the initialization of an SFI interface from a Reset state to a Connected state. In the particular example illustrated in Petition 870260023612, dated 03 / 23 / 2026, page 69 / 263 60 / 128 Figure 11 illustrates an exemplary initialization flow using initialization signals on a global channel of the SFI interface. As shown in Figure 11, the set of initialization signals may include a receiver disconnect NACK signal 1110, a receiver connect ACK signal 1115, and a transmitter connect request signal 1120. Additional signals are shown to illustrate specific features, including a receiver reset signal 1130 (to cause the agent to enter a reset condition), a transmitter reset signal 1135 (to cause the tissue to enter a reset condition). Also illustrated is a representation of at least one of the set of credit return signals for the SFI channels 1125 (e.g., the set of credit signals for one or more of the HDR and DATA channels).

[0087] In order to enter a connected state, when the transmitter is out of reset, it can assert the txcon_req 1120 signal to identify the request to the receiver. Similarly, when the receiver is out of reset, it waits for a connection request on the txcon_req 1120 signal. The assertion of the connection request can be an arbitrary number of cycles after the reset (e.g., 1130) assertion. Until the connection is complete, the txcon_req 1120 signal must remain and should only unassert as part of the disconnection flow. Upon receiving a connection request on the txcon_req 1120 signal, the receiver can assert the Petition 870260023612, dated 03 / 23 / 2026, pp. 70 / 263 61 / 128 signal rxcon ack 1115 to confirm the request. The rxcon ack 1115 signal can be asserted after receiver and transmitter resets, and the assertion of the txcon req 1120 signal. The rxcon ack 1115 signal must remain asserted and must be unasserted first only in a disconnect flow.

[0088] This sequence can allow the initial link state 1105 to progress from a Disconnected state to a Connecting state to the Connected state. Upon entering the Connected state (and sending the rxcon_ack signal), the receiver can immediately begin returning credits (e.g., on credit return wires 1125). In fact, the receiver can begin returning credits simultaneously with the assertion of the rxcon_ack signal 1115. Consequently, the transmitter (e.g., the agent) is prepared to accept credit returns upon assertion of the txcon_req signal 1120 (e.g., on clock cycle x4), for example, since credit returns can be observed before the observation of A2F_rxcon_ack due to intermediate temporary storage or clock crossings. After the minimum credits are received to send packets, the transmitter can begin sending packets or messages over the channel.The reconnection flow can be deployed similarly to the reset flow connection discussed in this document; however, to start a new credit initialization, the receiver will first reset its credit counters to reset values, and the transmitter will reset its counters. Petition 870260023612, dated 03 / 23 / 2026, page 78 / 263 62 / 128 available credits for zero, among other exemplary implementations.

[0089] With respect to Figure 12, an exemplary timing diagram 1200 is shown, which illustrates an example disconnect and reconnect flow for an exemplary SFI interface. In this example, the transmitter can de-assert the txcon req 1120 signal to facilitate a disconnect at time x3. In some deployments, to allow the disconnect to proceed, the rxdiscon nack 1110 signal must be de-asserted before the txcon_req 1120 signal is de-asserted. When a disconnect is requested, the transmitter should no longer send messages on any channel (e.g., indicated by the CHAN is valid bit assertion). Based on the transmitter initiating a disconnect flow, the receiver must decide whether to acknowledge (ACK) or de-acknowledge (NACK or reject) the disconnect.To confirm disconnection, the receiver can disclaim the rxcon_ack 1115 signal after ensuring that all pipelines are empty (e.g., on clock cycle x4), which marks entry into a disconnected state (as reflected by link status indicator 1105). In some instances, the receiver can also ensure that all credits have been returned.

[0090] Although diagram 1200 in Figure 12 illustrates an instance where a disconnect request was positively acknowledged by the receiver, Figure 13 illustrates a contrary example where the receiver responds with a negative acknowledgment (or NACK). For example, to send a negative acknowledgment, the receiver can, Petition 870260023612, dated 03 / 23 / 2026, p. 72 / 263 63 / 128 instead, assert the rxdiscon nack 1110 signal (e.g., on clock cycle x4). For example, negative confirmation may be selected if the receiver determines that it does not have the capacity to flush its pipelines without the risk of blocking, among other illustrative reasons. After the NACK, the transmitter must reaffirm the txcon req 1120 signal (e.g., on clock cycle x6). Upon observation of this effective confirmation by the transmitter of the receiver's NACK, the rxdiscon nack 1110 signal may be deaffirmed (e.g., as shown on clock cycle x6 in the example in Figure 13).

[0091] In some deployments, connection and disconnection flows are expected to complete within a few microseconds of initiation. In some deployments, a timeout may be set, explicitly or implicitly. For example, a receiver may be configured to respond with an ACK or NACK within a defined or recommended time window. For example, the agent, mesh, or system (e.g., SoC) may set a timeout or time window to enforce this expectation.

[0092] In some instances, an agent or mesh element may reboot while the SEI interface is in a connected state, resulting in a surprise reboot. For example, the defined or recommended flow may be to enter Disconnect before Reboot. As an example, an rxcon ack signal may make the 1^0 transition that occurs due to a surprise reboot on the receiver side of the link. Petition 870260023612, dated 03 / 23 / 2026, p. 70 / 263 64 / 128 while the transmitter's txcon req signal value is 1. In such a case, the transmitter may force itself into a disconnected state and reboot the initialization. If this occurs when the transmitter is in an idle state, it may recover without message loss. As another example of a surprise reboot, if the txcon_req signal transitions from 1 to 0 due to a surprise reboot on the transmitter side of the link while rxcon ack is 1, the standard disconnect flow may be followed. If this occurs when the receiver is in an idle state, the disconnect should receive Ack and cleanly achieve a disconnected state, as the transmitter remains in reboot. If the disconnect is Denied (NACK) by the receiver, however, a fatal or illegal link state may result (e.g., an unrecoverable error).In cases of surprise restarts, if traffic is active (i.e., not idle), a loss of protocol messages may result and could be fatal to continued normal operation.

[0093] As discussed above, an SFI interface in a system can be configurable according to a variety of parameters. For example, a set of parameters can be specifically defined according to the use case, resources, protocols, and topology of a given system, such as a particular SoC design. Such parameters can define, for example, the maximum number of headers that can be transmitted in a single cycle, the maximum header size, the maximum number of payloads of different packets that can be transmitted. Petition 870200023618, dated 03 / 23 / 2026, page 74 / 264 65 / 128 can be sent in a single cycle, among other illustrative parameters. Parameter values ​​can be defined and saved, for example, in a configuration record or other data structure for use and reference by the agent and mesh components connected through the interface. Table 6 presents an example of parameters that can be defined in an example of an SFI interface. TABLE 6: SUPPORTED PARAMETERS Parameter Description VT Width of tx_vendor_field VR Width of rx_vendor_field M Maximum number of headers that can be transmitted in a given cycle MAX_HDR_WIDTH Maximum size of 1 header in bytes. One header credit corresponds to MAX_HDR_WIDTH bytes of storage. A minimum and maximum of one credit is used per header transfer. H Total header width in bytes. It is MAX_HDR_WIDTH*M. MAX_FC_VC Maximum number of FC and VC ID combinations that can be received in 1 cycle. It is recommended that it be 1. This parameter applies to both HDR and DATA layers. D Total width of the data signal in bytes. This must be a multiple of 4. DS Maximum number of independent data packets that can be sent in 1 cycle. DATA_PASS_HDR If set to 1, TX may allow data to run before the corresponding header. If set to 0, TX will always send the header before the corresponding data.It is recommended that this parameter be set to 0, so that RX data tracking is simplified.

[0094] With reference to Figures 14A to 14B, simplified flowcharts 1400a and 14b are shown, which illustrate exemplary techniques for using an SFI interface, as discussed in the exemplary deployments in this document. For example, in the example in Figure 14A, an SFI interface can be composed of lanes assigned to the respective signals in a signal set to send a message to a Petition 870260023612, dated 03 / 23 / 2026, p. 72 / 263 66 / 128 receiver on a particular channel among the plurality of channels of the interface (e.g., Global, HDR, and DATA), as well as lanes assigned to signals to be received from the message receiver (e.g., credit return signals). A global channel may include multiple lanes for sending and receiving respective signals to control aspects of the interface that include interface initialization. In fact, initialization signals may be communicated 1405 on the interface to initialize 1410 the interface for sending messages from the interface channels (e.g., HDR and DATA). A packet may be identified 1415, which has been prepared by protocol layers of an agent or other logic on a device (e.g., an IP block, mesh block, sealing device, or other device) according to a particular streaming or upload / store protocol, such as PCIe or CXL.io, among other examples.The header and payload of the packet can be sent separately on dedicated header (HDR) and payload (DATA) channels of the interface. For example, the header can be sent on the header bus lanes of the header channel accompanied by header metadata sent on the HDR channel lanes dedicated to a header metadata signal. Similarly, the DATA channel can be used to send the payload data on the data bus lanes of the DATA channel, and corresponding payload metadata can be sent on other separate lanes of the DATA channel that deploys one or more. Petition 870200023618, dated 03 / 23 / 2026, page 76 / 263 67 / 128 more metadata signals for the DATA channel. In some deployments, to send a header or payload on the HDR or DATA channel, respectively, a valid signal can be sent in a dedicated set of one or more lanes of the corresponding channel. In some deployments, credit returns may be received by the packet sender corresponding to the respective credits used in each of the HDR and DATA channels, among other information and exemplary signals, which can be deployed on the HDR and DATA channels, as discussed in the examples above.

[0095] In the example in Figure 14B, techniques are illustrated associated with a receiver on an SFI interface. In some deployments, a single device may deploy a transmitter for a first instance of an SFI interface and a receiver side for a second, complementary instance of an SFI interface, among other exemplary configurations. In one example, a global channel may also be provided on the receiver side to communicate initialization signals to initialize the interface. After initialization, packet data may be received over the interface, which includes the payload data and packet header. For example, a packet header may be received in header channel lanes, along with header metadata received in separate metadata lanes from the header channel. The packet payload data may be received in lanes of a separate data channel.Payload metadata can be received 1465 times. Petition 870260023612, dated 03 / 23 / 2026, page 73 / 263 68 / 128 additional metadata lanes of the data channel to describe payload attributes (e.g., flow control information). The receiver can process the packet (e.g., temporary storage, associating a header with its packet, decoding the header, identifying payload boundaries sent in the data lanes, etc.) based on the payload and header metadata sent in the respective metadata lanes of the header and data channels. The receiver can also send credit returns in additional dedicated lanes of the data and header channels, among other exemplary functionality provided by the logic in the receiver.

[0096] Note that the apparatus, methods, and systems described above can be deployed in any electronic device or system, as mentioned above. As specific illustrations, the Figures below provide exemplary systems (e.g., SoCs, computing blocks, mesh blocks, etc.) to utilize the solutions described in this document. As the systems below are described in more detail, a number of different interconnections, use cases, topologies, and applications are revealed, described, and revisited from the discussion above. And, as is readily apparent, the advances described above can be applied to any of these interconnections, meshes, or architectures and their composite components.

[0097] With reference to Figure 15, a manifestation of a block diagram for a computing system that includes a multi-processor is represented. Petition 870200023618, dated 03 / 23 / 2026, page 78 / 263 69 / 128 cores. The 1500 processor includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system-on-a-chip (SOC), or other device for executing code. The 1500 processor, in one embodiment, includes at least two cores—cores 1501 and 1502, which may include asymmetric cores or symmetric cores (the embodiment illustrated). However, the 1500 processor may include any number of processing elements that may be symmetric or asymmetric.

[0098] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logic processor, a hardware thread, a core, and / or any other element capable of holding a state for a processor, such as an execution state or architecture state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any Petition 870260023612, dated 03 / 23 / 2026, page 79 / 263 70 / 128 number of other processing elements, such as hardware cores or threads.

[0099] A kernel often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to kernels, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and a kernel overlaps.A hardware core and thread are still often viewed by an operating system as individual logical processors, where the operating system has the ability to individually program operations on each logical processor.

[00100] The physical processor 1500, as illustrated in Figure 15, includes two cores—cores 1501 and 1502. Here, cores 1501 and 1502 are considered symmetrical cores, that is, cores with the same configurations, functional units, and / or logic. In another embodiment, core 1501 includes an out-of-order processor core, although core 1502 includes an in-order processor core. However, cores 1501 and 1502 can be individually Petition 870260023612, dated 03 / 23 / 2026, page 801611 71 / 128 selected from any type of kernel, such as a native kernel, a software-managed kernel, a kernel adapted to run a native instruction set architecture (ISA), a kernel adapted to run a translated instruction set architecture (ISA), a co-designed kernel, or another known kernel. In a heterogeneous kernel environment (i.e., asymmetric kernels), some form of translation, such as binary translation, may be used to program or execute code on one or both kernels. To further the discussion, the functional units illustrated in kernel 1501 are described in additional detail below, as the units in kernel 1502 operate in a similar manner in the represented mode.

[00101] As depicted, the 1501 core includes two hardware threads, 1501a and 1501b, which can also be referred to as hardware thread slots 1501a and 1501b. Therefore, software entities, such as an operating system, in one embodiment, potentially view the 1500 processor as four separate processors, that is, four logical processors or processing elements capable of executing four software threads simultaneously. As mentioned above, a first thread is associated with architecture state registers 1501a, a second thread is associated with architecture state registers 1501b, a third thread may be associated with architecture state registers 1502a, and a fourth thread may be... Petition 870260023612, dated 03 / 23 / 2026, page 78 / 263 72 / 128 associated with architecture state registers 1502b. Here, each of the architecture state registers (1301a, 1501b, 1502a, and 1502b) can be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1501a are replicated in architecture state registers 1501b, thus individual architecture contexts / states have the capacity to be stored for both logical processor 1501a and logical processor 1501b. In the 1501 core, other minor resources, such as instruction indicators and renaming logic in the 1530 allocator and renamer block, can also be replicated for threads 1501a and 1501b. Some resources, such as temporary reorder storage in the 1535 pickup / reorder unit, ILTB 1520, temporary load / store storage, and queues, can be shared via partitioning.Other resources, such as internal general-purpose records, page table base record(s), low-level data cache and data TLB 1515, execution unit(s) 1540 and out-of-order unit portions 1535 are potentially fully shared.

[00102] The 1500 processor often includes other resources, which may be fully shared, shared through partitioning, or dedicated by / to processing elements. Figure 15 illustrates a purely exemplary embodiment of a processor with logical resources / units. Petition 870260023612, dated 03 / 23 / 2026, page 83 / 263 72 / 128 associated with architecture state registers 1502b. Here, each of the architecture state registers (1301a, 1501b, 1502a, and 1502b) can be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1501a are replicated in architecture state registers 1501b, thus individual architecture contexts / states have the capacity to be stored for both logical processor 1501a and logical processor 1501b. In the 1501 core, other minor resources, such as instruction indicators and renaming logic in the 1530 allocator and renamer block, can also be replicated for threads 1501a and 1501b. Some resources, such as temporary reorder storage in the 1535 pickup / reorder unit, ILTB 1520, temporary load / store storage, and queues, can be shared via partitioning.Other resources, such as internal general-purpose records, page table base record(s), low-level data cache and data TLB 1515, execution unit(s) 1540 and out-of-order unit portions 1535 are shared in a potentially complete manner.

[00102] The 1500 processor often includes other resources, which may be fully shared, shared through partitioning, or dedicated by / to processing elements. Figure 15 illustrates a purely exemplary embodiment of a processor with logical resources / units. Petition 870200029918, dated 09 / 24 / 2020, page 89 / 264 73 / 128 illustrative of a processor. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not represented. As illustrated, core 1501 includes a representative and simplified out-of-order processor core (000). However, an in-order processor may be used in different modes. Core 000 includes a branch target temporary store 1520 to predict branches to be executed / considered and an instruction translation temporary store (I-TLB) 1520 to store address translation entries for instructions.

[00103] The 1501 core additionally includes the 1525 decoding module coupled to the 1520 fetch unit to decode fetched elements. The fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1501b, 1501b, respectively. Typically, the 1501 core is associated with a first ISA, which defines / specifies executable instructions in the 1500 processor. Often the machine code instructions that are part of the first ISA include an instruction portion (referred to as an opcode), which mentions / specifies an instruction or operation to be performed. The 1525 decoding logic includes a set of circuits that recognizes these instructions from their opcodes and passes the decoded instructions into the processing channel for processing as defined by the first ISA. For example, as discussed in more detail below, the Petition 870200029918, dated 09 / 24 / 2020, page 80 / 264 74 / 128 1525 decoders, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instructions. As a result of recognition through 1525 decoders, the 1501 architecture or kernel takes specific predefined actions to perform the tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. It should be noted that 1526 decoders, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous kernel environment, 1526 decoders recognize a second ISA (a subset of the first ISA or a distinct ISA).

[00104] In one example, the allocator and renamer block 1530 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1501a and 1501b potentially have out-of-order execution capability, where the allocator and renamer block 1530 also reserves other resources, such as temporary reorder stores to track instruction results. Unit 1530 may also include a register renamer to rename program / instruction reference registers to other registers internal to the processor 1500. The take-off / reorder unit 1535 includes components such as the aforementioned temporary reorder stores. Petition 870200029918, dated 09 / 24 / 2026, page 85 / 264 75 / 128 above, temporary load stores and temporary storage stores, to support out-of-order execution and subsequent in-order pickup of out-of-order executed instructions.

[00105] The 1540 execution unit (or units) block, in one embodiment, includes a scheduler unit for scheduling instructions / operations in execution units. For example, a floating-point instruction is scheduled in a port of an execution unit that has a floating-point execution unit available. Log files associated with the execution units are also included to store instruction processing results and information. Exemplary execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

[00106] The lower-level data cache and the Data Translation Temporary Library (D-TLB) 1550 are coupled to the execution unit (or units) 1540. The data cache should store recently used / operated elements, such as data operands, which are potentially retained in memory coherence states. The D-TLB should store recent virtual / linear-to-physical address translations. As a specific example, a processor might include a page table structure to break physical memory into a plurality of virtual pages. Petition 870200029918, dated 09 / 24 / 2020, page 80 / 264 76 / 128

[00107] Here, the 1501 and 1502 cores share access to higher-level or more advanced cache, such as a second-level cache associated with the 1510 on-chip interface. It should be noted that higher-level or more advanced refers to cache levels that extend from or move away from the execution unit (or units). In one embodiment, a higher-level cache is a last-level data cache—the last cache in the memory hierarchy in the 1500 processor—such as a second- or third-level data cache. However, the higher-level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—may preferably be coupled after the 1525 decoder to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e., a general instruction recognized by the decoders), which may be decoded into several micro-instructions (micro-operations).

[00108] In the configuration shown, the 1500 processor also includes an on-chip interface module 1510. Historically, a memory controller, which is described in more detail below, was included in a computing system external to the 1500 processor. In this scenario, the on-chip interface 1510 must communicate with devices external to the 1500 processor, such as the 1575 system memory, a chip set (which often includes a memory controller hub to connect to the 1575 memory and an I / O controller hub to connect peripheral devices), a hub Petition 870200029918, dated 09 / 24 / 2020, page 83 / 264 77 / 128 memory controller, a northbridge, or other integrated circuit. And in this scenario, the 1505 bus can include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent bus (e.g., cache-coherent), a layered protocol architecture, a differential bus, and a GTL bus.

[00109] 1575 memory can be dedicated to the 1500 processor or shared with other devices in a system. Common examples of 1575 memory types include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that the 1580 device may include a graphics accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I / O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

[00110] Recently, however, as more devices and logic are being integrated into a single die, such as a SoC, each of these devices can be incorporated into the 1500 processor. For example, in one embodiment, a memory controller hub is in the same package and / or die as the 1500 processor. Here, a portion of the core (a portion within the core) 1510 includes one or more controllers to interface with other devices, such as the 1575 memory or a 1580 graphics device. The configuration that includes an interconnect and controllers to do a Petition 870200029918, dated 09 / 24 / 2020, p. 88 / 264 78 / 128 interfacing with such devices is often referred to as an on-core configuration (or off-core configuration). As an example, the 1510 on-chip interface includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1505 for off-chip communication. Furthermore, in the SOC environment, even more devices, such as the network interface, coprocessors, 1575 memory, 1580 graphics processor, and any other known computer / interface devices, can be integrated into a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[00111] In one embodiment, the 1500 processor has the capability to execute a translator, optimization, and / or compiler code 1577 to compile, translate, and / or optimize application code 1576 to support the apparatus and methods described herein or to interface with them. A compiler typically includes a program or set of programs to translate source code / text into target code / text. Typically, program / application code compilation with a compiler is done in multiple stages and passes to transform high-level programming language code into low-level assembly or machine language code. In addition, single-pass compilers can still be used for simple compilation. A compiler can use any known compilation techniques and perform any known compiler operations. Petition 870200029918, dated 09 / 24 / 2020, p. 89 / 264 79 / 128 such as lexical analysis, preprocessing, analysis, semantic analysis, code generation, code transformation, and code optimization.

[00112] Larger compilers often include multiple phases, but these phases are most frequently included in two general phases: (1) a front-end, i.e., where syntactic processing, semantic processing, and some transformation / optimization may generally occur, and (2) a backend, i.e., where parsing, transformations, optimizations, and code generation generally occur. Some compilers refer to an intermediary that illustrates the blurring of delineation between a compiler's front-end and back-end. As a result, reference to a compiler's insertion, association, generation, or other operation may occur in any of the aforementioned phases or passages, as well as any other known phases or passages of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc.in one or more compilation phases, such as inserting calls / operations in a front-end compilation phase and then transforming the calls / operations into lower-level code during a transformation phase. It should be noted that during dynamic compilation, compiler code or dynamic optimization code may insert such operations / calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already existing code)... Petition 870200029918, dated 09 / 24 / 2020, page 80 / 264 (80 / 128 compiled) can be dynamically optimized during runtime. Here, the program code can include dynamic optimization code, binary code, or a combination of both.

[00113] Similar to a compiler, a translator, such as a binary translator, translates code in a static or dynamic manner to optimize and / or translate code. Therefore, reference to code execution, application code, program code, or other software environment may refer to: (1) execution of a compiler, code optimizer, or translator program (or programs) in a dynamic or static manner, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code that includes operations / calls, such as application code that has been optimized / compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software-related operations, or to optimize code; or (4) a combination thereof.

[00114] Referring now to Figure 16, a block diagram of an embodiment of a multi-core processor is shown. As shown in the embodiment of Figure 16, the 1600 processor includes multiple domains. Specifically, a 1630 core domain includes a plurality of 1630A to 1630N cores, a 1660 graphics domain includes one or more graphics engines that have a Petition 870200029918, dated 09 / 24 / 2020, page 87 / 264 81 / 128 media mechanism 1665, and a system agent domain 1610.

[00115] In various embodiments, the system agent domain 1610 manipulates power control and power management events, such that individual units of domains 1630 and 1660 (e.g., cores and / or graphics engines) are independently controllable to operate dynamically in an appropriate power mode / level (e.g., active, turbo, idle, hibernate, deep inactivity, or other Advanced Configuration Power Interface type state) in light of the activity (or inactivity) occurring in the given unit. Each of domains 1630 and 1660 can operate at a different voltage / power, and furthermore, the individual units within the domains potentially operate at different frequencies and voltages. Note that although only three domains are shown, the understanding of the scope of this disclosure is not limited to this, and additional domains may be present in other embodiments.

[00116] As shown, each 1630 core additionally includes low-level caches in addition to several execution units and additional processing elements. In the present context, the various cores are coupled to each other and to a shared cache memory that is formed from a plurality of units or slices of a 1640A to 1640N last-level cache (LLC); these LLCs often include storage controller functionality and Petition 870200029918, dated 09 / 24 / 2020, p. 88 / 264 82 / 128 cache and are shared between cores, as well as potentially between the graphics engine.

[00117] As noted, a 1650 ring interconnect couples the cores together and provides interconnection between the 1630 core domain, 1660 graphics domain, and 1610 agent circuit system, by means of a plurality of 1652A to 1652N ring stops, each in a coupling between a core and an LLC slice. As noted in Figure 16, the 1650 interconnect is used to carry various information, including address information, data information, acknowledgment information, and invalid / unvalidated information. Although a ring interconnect is illustrated, any known interconnect or matrix fabric can be used.As an illustrative example, some of the fabrics discussed above (e.g., another matrix interconnect, system-on-a-chip (OSF) fabric, an Advanced Microcontroller Bus Architecture (AMBA) interconnect, a multidimensional mesh fabric, or another known interconnect architecture) can be used in a similar manner.

[00118] As further depicted, the system agent domain 1610 includes the display mechanism 1612 which must provide control and an interface to an associated display. The system agent domain 1610 may include other units, such as: an integrated memory controller 1620 which provides an interface to a memory system (e.g., a DRAM deployed with multiple DIMMs); ​​coherence logic 1622 for Petition 870200029918, dated 09 / 24 / 2020, page 89 / 264 83 / 128 perform memory coherence operations. Multiple interfaces may be present to enable interconnection between the processor and another set of circuits. For example, in one embodiment, at least one Direct Media Interface (DMI) 1616 is provided as well as one or more PCIe™ 1614 interfaces. The display mechanism and these interfaces typically couple to memory via a PCIe™ 1618 bridge. In addition, to provide communication between other agents, such as additional processors or another set of circuits, one or more other interfaces may be provided.

[00119] Referring to Figure 17, a block diagram of a representative core is shown; specifically, logical blocks of a core back-end, such as core 1630 of Figure 16. In general, the structure shown in Figure 17 includes an out-of-order processor that has a front-end unit 1770 used to fetch input instructions, perform various instruction / processing operations (e.g., caching, decoding, branch prediction, etc.) and pass along an out-of-order mechanism (000) 1780. The 000 mechanism 1780 performs further processing on the decoded instructions.

[00120] Specifically, in the embodiment of Figure 17, the out-of-order mechanism 1780 includes an allocation unit 1782 to receive decoded instructions, which may be in the form of one or more microinstructions or uops, from the front-end unit 1770, and allocate them. Petition 870200029918, dated 09 / 24 / 2020, page 90 / 264 84 / 128 to allocate resources, such as registers and so on. Next, instructions are given to a reservation station 1784, which reserves resources and schedules them for execution in one of a plurality of execution units 1786A to 1786N. Several types of execution units may be present, including, for example, arithmetic logic units (ALUs), load and store units, vector processing units (VPUs), floating-point execution units, among others. The results from these different execution units are given to a temporary reordering store (ROB) 1788, which takes the unordered results and returns them to correct the program order.

[00121] Referring again to Figure 17, it can be seen that both the front-end unit 1770 and the out-of-order mechanism 1780 are coupled to different levels of a memory hierarchy. Specifically, an instruction-level cache 1772 is shown which, in turn, couples to an intermediate-level cache 1776 which, in turn, couples to a last-level cache 1795. In one embodiment, the last-level cache 1795 is implemented in an on-chip unit (sometimes called an uncore) 1790. As an example, the unit 1790 is similar to the system agent 1710 in Figure 17. As discussed above, the uncore 1790 communicates with the system memory 1799, which, in the illustrated embodiment, is implemented by ED RAM. It is also observed that the various 1786 execution units within the out-of-order 1780 mechanism are in communication with a cache of Petition 870200029918, dated 09 / 24 / 2026, p. 95 / 264 85 / 128 first level 1774 which is also in communication with intermediate level cache 1776. It is also observed that the additional cores 1730N-2 to 1730N can couple to LLC 1795. Although shown at this high level in the modality of Figure 17, it is understood that several additional changes and components may be present.

[00122] Referring to Figure 18, a block diagram of an exemplary computer system formed with a processor that includes execution units to execute an instruction, wherein one or more of the interconnections deploy one or more features in accordance with an embodiment of the present disclosure are illustrated. The 1800 system includes a component, such as an 1802 processor, to employ execution units that include logic to perform algorithms to process data, according to the present disclosure, as in the embodiment described herein. In one embodiment, the sample 1800 system runs a version of an operating system and software, including and providing corresponding graphical user interfaces, may also be used. However, the embodiments of the present disclosure are not limited to any specific combination of hardware and software circuitry.

[00123] The embodiments are not limited to computer systems. The alternative embodiments of the present disclosure may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include Petition 870200029918, dated 09 / 24 / 2026, page 96 / 264 86 / 128 mobile phones, Internet protocol devices, digital cameras, digital personal assistants (PDAs), and portable PCs. Embedded applications may include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, network computers (NetPCs), converters, network hubs, wide area network (WAN) switches, or any other system that can perform one or more instructions according to at least one mode.

[00124] In this illustrated embodiment, the 1802 processor includes one or more 1808 execution units to implement an algorithm that must perform at least one instruction. An embodiment may be described in the context of a single-processor server or desktop system, but alternative embodiments may be included in a multiprocessor system. The 1800 system is an example of a “hub” system architecture. The 1800 computer system includes an 1802 processor to process data signals. The 1802 processor, as an illustrative example, includes a microprocessor computer with a complex instruction set (CISC), a microprocessor with a reduced instruction set (RISC), a very long instruction word (VLIW) microprocessor, a processor that implements a combination of instruction sets, or any other processing device, such as a digital signal processor, for example.The 1802 processor is coupled to an 1810 processor bus that transmits data signals between the 1802 processor and other components in the 1800 system. The elements of... Petition 870200029918, dated 09 / 24 / 2020, page 93 / 264 87 / 128 1800 system (e.g., graphics accelerator 1812, memory controller hub 1816, memory 1820, I / O controller hub 1825, wireless transceiver 1826, BIOS Flash 1828, network controller 1834, audio controller 1836, serial expansion port 1838, I / O controller 1840, etc.) perform their conventional functions which are well known to those familiar with the art.

[00125] In one embodiment, the 1802 processor includes an internal Level 1 (L1) cache memory 1804. Depending on the architecture, the 1802 processor may have a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches depending on the deployment and particular needs.The 1806 log file is for storing different types of data in various registers, including integer registers, floating-point registers, vector registers, deposited registers, shadow registers, checkpoint registers, status registers, and instruction indicator registers.

[00126] The 1808 execution unit, which includes logic for performing integer and floating-point operations, also resides in the 1802 processor. The 1802 processor, in one embodiment, includes a microcode ROM (ucode) to store the microcode, which, when executed, must perform algorithms for certain macroinstructions or handle complex scenarios. Here, the microcode is potentially updatable to handle logic faults / corrections for the 1802 processor. For one embodiment, the 1808 execution unit includes logic Petition 870200029918, dated 09 / 24 / 2020, page 98 / 264 88 / 128 to handle a packed instruction set 1809. By including the packed instruction set 1809 in the instruction set of a general-purpose processor 1802, along with the associated circuitry to execute the instructions, operations used by many multimedia applications can be performed using packed data in a general-purpose processor 1802. Thus, many multimedia applications are accelerated and run more efficiently by using the full width of a processor data bus to perform operations on packed data. This potentially eliminates the need to transfer smaller units of data across the processor data bus to perform one or more operations, one data element at a time.

[00127] Alternative embodiments of an 1808 execution unit may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. The 1800 system includes an 1820 memory. The 1820 memory includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another memory device. The 1820 memory stores instructions and / or data represented by data signals that must be executed by the 1802 processor.

[00128] Note that any of the features or aspects mentioned above of this disclosure and Petition 870200029918, dated 09 / 24 / 2020, page 99 / 264 89 / 128 solutions can be used in one or more of the interconnections illustrated in Figure 18. For example, a grid interconnect (GDI), which is not shown, for coupling internal processor units 1802 implements one or more aspects of the embodiments described above. Alternatively, the embodiments can be associated with a processor bus 1810 (e.g., another known high-performance computing interconnect), a high-bandwidth memory path 1818 to memory 1820, a point-to-point link for graphics accelerator 1812 (e.g., a fabric conforming to Peripheral Component Interconnect Express (PCIe)), a controller hub interconnect 1822, an I / O interconnect, or another interconnect (e.g., USB, PCI, PCIe) to couple the other illustrated components.Some examples of such components include the audio controller 1836, firmware hub (flash BIOS) 1828, wireless transceiver 1826, data storage 1824, legacy I / O controller 1810 containing user input and keyboard interface 1842, a serial expansion port 1838 such as Universal Serial Bus (USB), and a network controller 1834. The data storage device 1824 may comprise a hard disk, a floppy disk, a CD-ROM device, a flash memory device, or other mass storage devices.

[00129] Referring now to Figure 19, a block diagram of a second 1900 system is shown according to an embodiment of the present disclosure. As shown in Figure 19, the system of IMçjiãDSOTMflinWÜ28,de EMWfflQQ,^. MMQM The 90 / 128 multiprocessor 1900 is a point-to-point interconnect system and includes a first 1970 processor and a second 1980 processor coupled through a 1950 point-to-point interconnect. Each of the 1970 and 1980 processors may be some version of a processor. In one embodiment, 1952 and 1954 are part of a coherent serial point-to-point interconnect mesh, such as a high-performance architecture.

[00130] Although shown with only two processors in the 1970s and 1980s, it should be understood that the scope of this disclosure is not limited in this way. In other embodiments, one or more additional processors may be present in a given processor.

[00131] Processors 1970 and 1980 are shown with integrated memory controller units 1972 and 1982, respectively. Processor 1970 also includes point-to-point (PP) interfaces 1976 and 1978 as part of its bus controller units; similarly, the second processor 1980 includes PP interfaces 1986 and 1988. Processors 1970 and 1980 can exchange information via a point-to-point (PP) interface 1950 using PP interface circuits 1978 and 1988. As shown in Figure 19, IMCs 1972 and 1982 couple the processors to their respective memories, namely a memory 1932 and a memory 1934, which may be portions of system memory fixed locally to the respective processors.

[00132] The 1970s and 1980s processors each exchange information with a 1990s chipset through interfaces Pffifliçjão8OT2W1^^ 1MW2WÍ),gí& ttUBl 91 / 128 Individual P chips 1952, 1954 using point-to-point interface circuits 1976, 1994, 1986, 1998. Chipset 1990 also exchanges information with a high-performance graphics circuit 1938 via an interface circuit 1992 over a high-performance graphics interconnect 1939.

[00133] A shared cache (not shown) may be included in either processor or be outside both processors; still connected with the processors via PP interconnects, so that either or both processors' local cache information may be stored in the shared cache if a processor is placed in a low-power mode.

[00134] The 1990 chipset can be coupled to a first 1916 bus via a 1996 interface. In one embodiment, the first 1916 bus can be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or other third-generation I / O interconnect bus, although the scope of the present disclosure is not limited to the same.

[00135] As shown in Figure 19, several I / O devices 1914 are coupled to the first bus 1916, along with a bus bridge 1918 that couples the first bus 1916 to a second bus 1920. In one embodiment, the second bus 1920 includes a low pin count (LPC) bus. Several devices are coupled to a second bus 1920 that includes, for example, a IMçjítoSOTMflinW1X.de· J34f0923IE20,ipág. H8WH 92 / 128 keyboard / mouse 1922, communication devices 1927, and the data storage unit 1928 as a magnetic disk drive or other mass storage device, which often includes code 1930, in one embodiment. Additionally, an audio I / O 1924 is shown coupled to the second bus 1920. Note that other architectures are possible, in which the included components and interconnection architectures vary. For example, instead of the point-to-point architecture of Figure 19, a system may deploy a multi-drop bus or other architecture.

[00136] Turning next to Figure 20, an embodiment of a system-on-a-chip (SOC) design conforming to the above disclosure is represented. As a specific illustrative example, the SOC 2000 is included in the user equipment (UE). In one embodiment, UE refers to any device to be used by an end user to communicate, such as a mobile phone, smartphone, tablet computer, ultra-thin notebook computer, notebook computer with broadband adapter, or any other similar communication device. Typically, a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

[00137] In the present context, the SOC 2000 includes 2 cores — 2006 and 2007. Similar to the discussion above, the 2006 and 2007 cores may conform to an Instruction Set Architecture, such as a processor based on Intel® Core™ Architecture, a processor from the ffiaiçjãoSTüKwi^^mwssps,,^ 93 / 128 Advanced Micro Devices, Inc. (AMD), a MIPS-based processor, an ARM-based processor model, or a customer thereof, as well as their licensees or adherents. Cores 2006 and 2007 are coupled to cache control 2008, which is associated with a bus interface unit 2009 and L2 cache 2011 to communicate with other parts of the system 2000. Interconnect 2010 includes an on-chip interconnect, such as IOSF, AMBA, or another interconnect discussed above, which potentially implements one or more aspects of what is described herein.

[00138] Interface 2010 provides communication channels to other components, such as a Subscriber Identity Module (SIM) 2030 for interfacing with a SIM card, a boot ROM 2035 for retaining the boot code for execution through cores 2006 and 2007 for starting and initializing the SOC 2000, an SDRAM controller 2040 for interfacing with external memory (e.g., DRAM 2060), a flash controller 2045 for interfacing with non-volatile memory (e.g., Flash 2065), a peripheral controller 2050 (e.g., the Serial Peripheral Interface) for interfacing with peripherals, video codecs 2020 and video interface 2025 for displaying and receiving input (e.g., touch-enabled input), GPU 2015 for performing graphics-related computations, etc. Any of these interfaces can incorporate aspects of the modalities described in this document. Petition 870200029918, dated 09 / 24 / 2020, page 104 / 264 94 / 128

[00139] Additionally, the system illustrates peripherals for communication, such as a Bluetooth module 2070, 3G modem 2075, GPS 2085 and Wi-Fi 2085. Note that, as stated above, a UE includes a radio for communication. As a result, not all of these peripheral communication modules are required. However, in a UE, a part that forms a radio for external communication must be included.

[00140] Although the present revelation has been described with respect to a limited number of modalities, those skilled in the art will find numerous modifications and variations of such modalities. It is intended that the appended claims cover all such modifications and variations as are encompassed by the true spirit and scope of this present revelation.

[00141] A project can go through several stages, from creation to simulation to manufacturing. The data representing a project can represent the project in numerous ways. First, as is useful in simulations, hardware can be represented using a hardware description language or another functional description language. Additionally, a circuit-level model with logic gates and / or transistors can be produced at some stages of the design process. Furthermore, most projects, at some stage, reach a data level that represents the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the Petition 870260029918, dated 09 / 24 / 2020, page 105 / 264 95 / 128 data representing the hardware model may be data specifying the presence or absence of various features in different masking layers used to produce the integrated circuit. In any design representation, the data may be stored in any form of machine-readable media. A memory or magnetic or optical storage such as a disk may be a machine-readable medium for storing information transmitted via modulated electrical or magnetic wave or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, until an electrical signal is copied, loaded into intermediate memory, or retransmitted, a new copy is produced.Therefore, a communications provider or a network provider may store on tangible, machine-readable media, at least temporarily, an item, such as information encoded in a carrier wave, that incorporates techniques of embodiments of the present disclosure.

[00142] A module as used herein refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-temporary medium for storing code adapted to be executed by the microcontroller. Therefore, reference to a module, in one embodiment, refers to hardware that is specifically configured to recognize and / or execute code to be retained on a non-temporary medium. Furthermore, in another embodiment, the use. Petition 870200029918, dated 09 / 24 / 2020, page 102 / 264 96 / 128 of a module refers to the non-transient medium, including the code, that is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) can refer to the combination of the microcontroller and the non-transient medium. Frequently, the module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[00143] The use of the phrase "configured to," in one embodiment, refers to arranging, assembling, manufacturing, offering for sale, importing, and / or designing a device, hardware, logic, or element to perform a designated or determined task. In this example, a device or element thereof that is not yet operating is "configured to" perform a designed task if it is designed, coupled, and / or interconnected to perform said designed task. By way of illustration only, a logic gate can provide a 0 or a 1 during operation. However, a logic gate "configured to" provide an enable signal to a clock does not include any logic gate that can provide a 1 or a 0. Instead, the logic gate Petition 870200029918, dated 09 / 24 / 2020, page 106 / 264 97 / 128 is coupled in some way that during operation, the output of 1 or 0 is to enable the clock. It is noted again that the use of the term configured does not require operation, but rather focuses on the latent state of a device, hardware, and / or element, where in the latent state, the device, hardware, and / or element is designed to perform a particular task when the device, hardware, and / or element is in operation.

[00144] Furthermore, the use of the phrases “capable of / for” and or “operable for” and the preposition “for” in a modality refers to some device, logic, hardware and / or element designed in such a way as to enable the use of the device, logic, hardware and / or element in a specific manner. It is observed that the use of for, capable of or operable for in a modality refers to the latent state of a device, logic, hardware and / or element, in which the device, logic, hardware and / or element is not in operation, but is designed in such a way as to enable the use of a device in a specific manner.

[00145] A value, as used in this document, includes any known representation of a number, a state, a logic state, or a binary logic state. Often, the use of logic levels, logic values, or logic values ​​is also referred to as l's and 0's, which simply represent binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or Petition 870200029918, dated 09 / 24 / 2020, page 108 / 264 98 / 128 a flash cell, can have the capacity to hold a single logical value or multiple logical values. However, other representations of values ​​in computer systems have been used. For example, the decimal number ten can also be represented with a binary value equal to 1.010 and a hexadecimal letter A. Therefore, a value includes any representation of information that can be retained in a computer system.

[00146] Furthermore, states can be represented by values ​​or portions of values. For example, a first value, such as a logical zero, can represent a default or initial state, while a second value, such as a logical zero, can represent a non-default state. Additionally, the terms reset and set, in one embodiment, refer to a default value and an updated value or updated state, respectively. For example, a default value potentially includes a high logical value, i.e., reset, while an updated value potentially includes a low logical value, i.e., set. It appears that any combination of values ​​can be used to represent any number of states.

[00147] The types of methods, hardware, software, firmware, or code sets presented above can be implemented by means of instructions or code stored on a machine-accessible, machine-readable, machine-accessible, or computer-readable medium that is executable by a processing element. A non-transient machine-readable / accessible medium includes any mechanism that provides Petition 870200029918, dated 09 / 24 / 2020, page 105 261 99 / 128 (i.e., stores and / or transmits) information in a machine-readable form, such as a computer or electronic system. For example, non-transient machine-accessible media includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for retaining information received from transient (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which should be distinguished from non-transient media that can receive information from the same.

[00148] The instructions used to perform the disclosure modalities may be stored within a system memory, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions may be distributed over a network or via other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable form (e.g., a computer), but is not limited to, floppy disks, optical discs, Compact Discs, Read-Only Memory (CD-ROMs), and magnetic-optical discs, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Programmable Read-Only Memory. Petition 870200029918, dated 09 / 24 / 2020, page 106 / 264 100 / 128 Erasable (EEPROM), optical or magnetic cards, flash memory, or tangible, machine-readable storage used in the transmission of information over the Internet via signals propagated electrically, optically, acoustically, or otherwise (e.g., carrier waves, infrared signals, digital signals, etc.). Consequently, computer-readable media includes any type of tangible machine-readable media suitable for storing or transmitting electronic instructions or information in a machine-readable form (e.g., a computer).

[00149] The following examples refer to embodiments in accordance with this Descriptive Report.Example 1 is an apparatus that includes: a set of protocol circuits for deploying a load / store interconnection protocol; and a set of interface circuits for deploying an interface for coupling to a mesh, wherein the interface includes: a header channel deployed in a first subset of a plurality of physical lanes, wherein the first subset of lanes includes first lanes for loading a packet header based on the interconnection protocol and second lanes for loading metadata for the header; and a data channel deployed in a second separate subset of the plurality of physical lanes, wherein the second subset of lanes includes third lanes for loading a packet payload and fourth lanes for loading metadata for the payload. Petition 870200029918, dated 09 / 24 / 2020, p. 107 / 264 101 / 128

[00150] Example 2 includes the subject matter of Example 1, wherein headers must be transmitted through the header channel in a single clock cycle, and payloads are transmissible through multiple clock cycles.

[00151] Example 3 includes the subject matter of Example 2, wherein the first subset of lanes additionally includes fifth lanes to carry another header from another packet in the header channel and sixth lanes to carry metadata for the other header, the header and the other channel must be transmitted together in a single clock cycle in the header channel.

[00152] Example 4 includes the subject matter of Example 3, in which, in a subsequent clock cycle, both the first and fifth lanes are used to load a third header of a third packet, and the size of the third header is larger than the header and the other header.

[00153] Example 5 includes the subject matter of any of Examples 1 through 4, wherein the header channel additionally includes a valid header signal in one of the first subset of lanes to identify valid header data in the first lanes, and the data channel additionally includes a valid data signal in one of the second subset of lanes to identify valid payload data in the third lanes.

[00154] Example 6 includes the material from Example 5, where the valid header signal is to identify Petition 870200029918, dated 09 / 24 / 2020, p. 108 / 264 102 / 128 additionally identifies valid metadata in the second lanes, and the valid data signal is to additionally identify valid metadata in the fourth lanes.

[00155] Example 7 includes the subject matter of any of Examples 1 through 6, wherein the second subset of lanes additionally includes fifth lanes to carry a start of the data signal to indicate a start of the payload on the data channel, and the start of the data signal is asserted on a particular clock cycle to identify a first portion of the third lanes used in the particular clock cycle to carry the start of the payload bytes.

[00156] 0 Example 8 includes the subject matter of Example 7, wherein the second subset of lanes additionally includes sixth lanes to carry an end-of-signal data to indicate the final bytes of the payload on the data channel, and the end-of-signal data is asserted in a subsequent clock cycle to identify a second portion of the third lanes used in the subsequent clock cycle to carry the final bytes of the payload.

[00157] Example 9 includes the material from any of examples 1 through 8, where the first subset of lanes additionally includes fifth lanes for carrying credit returns to the header channel, and the second subset of lanes additionally includes sixth lanes for carrying credit returns to the data channel. Petition 870200029918, dated 09 / 24 / 2020, p. 109 / 264 103 / 128

[00158] Example 10 includes the material from Example 9, where credits for the header channel or credits for the data channel include shared credits.

[00159] Example 11 includes the subject matter of any of Examples 1 through 10, wherein the metadata for the header or the metadata for the payload identifies flow control information for the packet.

[00160] Example 12 includes the subject matter of Example 11, where flow control information is unique to the packet on the interface during transmission of the header and payload on the interface.

[00161] Example 13 includes the subject matter of Example 12, wherein the flow control information includes a combination of a flow control class identifier and a virtual channel identifier for the packet.

[00162] Example 14 includes the subject matter of Example 13, wherein the interface defines a maximum number of different flow control class identifier-virtual channel identifier combinations for packets sent on the interface during a given clock cycle.

[00163] Example 15 includes the subject matter of any of Examples 11-14, wherein the metadata for the header additionally includes parity information, header size information, and indicates whether payload data is associated with the header.

[00164] Example 16 includes the subject matter of any of Examples 1 through 15, wherein the interface additionally includes a global channel deployed in a third subset of the plurality of physical lanes, wherein the Petition 870200029918, dated 09 / 24 / 2020, page 110 / 264 The 104 / 128 global channel is for carrying control signals to the interface.

[00165] Example 17 includes the subject matter of Example 16, where the control signals include a set of initialization signals for use in connecting and disconnecting flows to the interface.

[00166] Example 18 includes the material from Example 17, where the connection and disconnection flows conform to an initialization state machine, and the transitions between states defined in the initialization state machine are caused by the values ​​of the initialization signal set.

[00167] Example 19 includes the subject matter of any of Examples 1 through 18, where a plurality of headers must be loaded into the header channel before the payload transmission is completed.

[00168] Example 20 includes the subject matter of any of Examples 1 to 19, wherein the interface includes a first instance of the interface for sending packets to the mesh, and the device additionally includes a second instance of the interface for receiving packets from the mesh, wherein the second instance of the interface includes a second header channel and a second data channel.

[00169] Example 21 includes the subject matter of Example 20, additionally includes a memory to deploy a temporary receiver storage for the second instance of the interface, where the temporary receiver storage supports credit sharing between flow control classes or virtual channels. Petition 870200029918, dated 09 / 24 / 2020, pp. 115 / 264 105 / 128

[00170] Example 22 includes the subject matter of any of Examples 1 through 21, wherein the load / store interconnect protocol includes a Peripheral Component Interconnect Express (PCIe) protocol.

[00171] Example 23 includes the subject matter of Example 22, where the PCIe protocol includes PCIe generation 6.

[00172] Example 24 includes the subject matter of any of Examples 1 through 23, wherein the load / store interconnect protocol includes a Compute Express Link (CXL) protocol, and the CXL protocol includes CXL.io.

[00173] Example 25 includes the subject matter of any of Examples 1 through 24, wherein the mesh includes an interconnection mesh of a system-on-a-chip (SoC) device, and the device additionally includes a set of computing circuits for deploying a block of the SoC.

[00174] Example 26 is an apparatus that includes: a set of mesh circuits for deploying at least a portion of a system's interconnection mesh; and a set of interface circuits for deploying an interface for coupling to a computing device, wherein the interface includes: a header channel deployed in a first subset of a plurality of physical lanes, wherein the first subset of lanes includes first lanes for carrying a packet header based on the interconnection protocol and second lanes for carrying metadata for the header; and a data channel deployed in a second separate subset of the plurality of physical lanes, wherein the second subset of lanes includes third lanes for. Petition 870200029918, dated 09 / 24 / 2020, p. 112 / 264 106 / 128 load a payload from the package and fourth lanes to load metadata for the payload.

[00175] Example 27 includes the subject matter of Example 26, in that headers must be transmitted through the header channel in a single clock cycle, and payloads are transmissible through multiple clock cycles.

[00176] Example 28 includes the subject matter of Example 27, wherein the first subset of lanes additionally includes fifth lanes to carry another header from another packet in the header channel and sixth lanes to carry metadata for the other header, the header and the other channel must be transmitted together in a single clock cycle in the header channel.

[00177] Example 29 includes the subject matter of Example 28, in which, in a subsequent clock cycle, both the first and fifth lanes are used to load a third header of a third packet, and the size of the third header is larger than the header and the other header.

[00178] Example 30 includes the subject matter of any of Examples 26 to 29, wherein the header channel additionally includes a valid header signal in one of the first subset of lanes to identify valid header data in the first lanes, and the data channel additionally includes a valid data signal in one of the second subset of lanes to identify valid payload data in the third lanes. Petition 870200029918, dated 09 / 24 / 2020, pp. 116 / 264 107 / 128

[00179] Example 31 includes the material from Example 30, where the valid header signal is to further identify valid metadata in the second lanes, and the valid data signal is to further identify valid metadata in the fourth lanes.

[00180] Example 32 includes the subject matter of either of Examples 26 to 31, wherein the second subset of lanes additionally includes fifth lanes to carry a start of the data signal to indicate a start of the payload on the data channel, and the start of the data signal is asserted on a particular clock cycle to identify a first portion of the third lanes used in the particular clock cycle to carry the start of the payload bytes.

[00181] Example 33 includes the subject matter of Example 32, wherein the second subset of lanes additionally includes sixth lanes to carry an end-of-signal data to indicate the final bytes of the payload on the data channel, and the end-of-signal data is asserted in a subsequent clock cycle to identify a second portion of the third lanes used in the subsequent clock cycle to carry the final bytes of the payload.

[00182] Example 34 includes the material from either of Examples 26 to 33, where the first subset of lanes additionally includes fifth lanes for carrying credit returns to the header channel, and the second subset of lanes additionally includes sixth lanes for carrying credit returns to the data channel. Petition 870200029918, dated 09 / 24 / 2020, p. 118 / 264 108 / 128

[00183] Example 35 includes the material from Example 34, where credits for the header channel or credits for the data channel include shared credits.

[00184] 0 Example 36 includes the subject matter of either Examples 26 to 35, wherein the metadata for the header or the metadata for the payload identifies flow control information for the packet.

[00185] Example 37 includes the subject matter of Example 36, where flow control information is unique to the packet on the interface during transmission of the header and payload on the interface.

[00186] Example 38 includes the subject matter of Example 37, wherein the flow control information includes a combination of a flow control class identifier and a virtual channel identifier for the packet.

[00187] Example 39 includes the subject matter of Example 38, wherein the interface defines a maximum number of different flow control class identifier-virtual channel identifier combinations for packets sent on the interface during a given clock cycle.

[00188] Example 40 includes the subject matter of any of Examples 36 to 39, wherein the metadata for the header additionally includes parity information, header size information, and indicates whether payload data is associated with the header.

[00189] Example 41 includes the subject matter of any of Examples 26 to 40, wherein the interface additionally includes a global channel deployed on a third subset of the plurality of physical lanes, wherein the Petition 870200029918, dated 09 / 24 / 2020, pp. 115 / 264 The 109 / 128 global channel is for carrying control signals to the interface.

[00190] Example 42 includes the subject matter of Example 41, where the control signals include a set of initialization signals for use in connecting and disconnecting flows to the interface.

[00191] Example 43 includes the subject matter of Example 42, where the connection and disconnection flows conform to an initialization state machine, and the transitions between states defined in the initialization state machine are caused by the values ​​of the initialization signal set.

[00192] 0 Example 44 includes the subject matter of any of Examples 26 to 43, where a plurality of headers must be loaded into the header channel before payload transmission is completed.

[00193] Example 45 includes the subject matter of any of Examples 26 to 44, wherein the interface includes a first instance of the interface for sending packets to the mesh, and the device additionally includes a second instance of the interface for receiving packets from the mesh, wherein the second instance of the interface includes a second header channel and a second data channel.

[00194] Example 46 includes the subject matter of Example 45, additionally includes a memory to deploy a temporary receiver storage for the second instance of the interface, where the temporary receiver storage supports credit sharing between flow control classes or virtual channels. Petition 870200029918, dated 09 / 24 / 2020, pp. 120 / 264 110 / 128

[00195] Example 47 includes the subject matter of any of Examples 26 through 46, wherein the load / store interconnect protocol includes a Peripheral Component Interconnect Express (PCIe) protocol.

[00196] Example 48 includes the subject matter of Example 47, where the PCIe protocol includes PCIe generation 6.

[00197] Example 49 includes the subject matter of either of Examples 26 to 28, wherein the load / store interconnect protocol includes a Compute Express Link (CXL) protocol, and the CXL protocol includes CXL.io.

[00198] Example 50 includes the subject matter of any of Examples 26 through 49, wherein the system includes a system-on-a-chip (SoC) device, and the computing device includes a block of the SoC device.

[00199] Example 51 is a method that includes: receiving a packet header from a device through an interface, wherein the interface includes a header channel deployed on a first plurality of physical lanes and a data channel deployed on a second plurality of separate physical lanes, wherein the header is received on a first subset of the first plurality of lanes; receiving header metadata for the header on a second subset of the first plurality of lanes from the header channel; receiving packet payload data from the device on the interface's data channel, wherein the payload data is received on a first subset of the second plurality of lanes; receiving payload metadata for the payload data on Petition 870200029918, dated 09 / 24 / 2020, pp. 127 / 264 111 / 128 a second subset of the second lane plurality; and determine that the payload data is associated with the header based on the header metadata and payload metadata.

[00200] Example 52 includes the material from Example 51, including additionally decoding the header based on the header metadata.

[00201] Example 53 includes the subject matter of either Examples 51 to 52, including additionally: sending header credit returns to the device in a third subset of the first lane plurality, wherein the header credit returns include credit returns for the header channel; and sending data credit returns to the device in a third subset of the second lane plurality, wherein the data credit returns include credit returns for the data channel.

[00202] 0 Example 54 includes the material from Example 53, where header credit returns or data credit returns include shared credits.

[00203] 0 Example 55 includes the subject matter of any of Examples 51 to 54, wherein the header includes a first header of a first packet, the first header is received from the device via the data channel in a particular clock cycle, and the method additionally includes receiving a second header of a second packet in the first lane plurality in the particular clock cycle.

[00204] Example 56 includes the subject matter of Example 55, including additionally receiving header metadata. Petition 870200029918, dated 09 / 24 / 2020, pp. 128 / 264 112 / 128 for the second packet in a third subset of the first lane plurality, where the header metadata for the first and second headers are both received in the particular clock cycle.

[00205] Example 57 includes the subject matter of Example 55, including additionally receiving, in a subsequent clock cycle, a third header from a third packet, wherein the third header is loaded into the lanes used to load the first header and a portion of the lanes used to load the second header.

[00206] Example 58 includes the subject matter of any of Examples 51 to 57, including additionally: identifying the assertion of a valid header signal in a valid signal lane in the first plurality of lanes, wherein the valid header signal identifies that valid header data is sent in the first subset of the first plurality of lanes; and identifying the assertion of a valid data signal in a valid signal lane in the second plurality of lanes, wherein the valid data signal identifies that valid payload data is sent in the first subset of the second plurality of lanes.

[00207] Example 59 includes the subject matter of Example 58, wherein the valid header signal is to further identify valid metadata in the second subset of the first plurality of lanes, and the valid data signal is to further identify valid metadata in the second subset of the second plurality of lanes. Petition 870200029918, dated 09 / 24 / 2020, pp. 129 / 264 113 / 128

[00208] Example 60 includes the subject matter of either of Examples 51-59, including additionally: receiving a data signal start on a third subset of the second plurality of lanes deploying the data channel, wherein the data signal start indicates a payload start on the data channel, and the data signal start is asserted on a particular clock cycle to identify a first portion of the first subset of the second plurality of lanes used on the particular clock cycle to load the start of the payload bytes.

[00209] 0 Example 61 includes the subject matter of Example 60, including additionally: receiving an end of the data signal in a fourth subset of the second plurality of lanes that deploys the data channel, wherein the end of the data signal is asserted in a subsequent clock cycle to identify a corresponding portion of the first subset of the second plurality of lanes used in the subsequent clock cycle to load the final bytes of the payload.

[00210] Example 62 includes the subject matter of either Examples 51 to 61, wherein the header metadata or the data metadata identifies the flow control information for the packet.

[00211] Example 63 includes the subject matter of Example 62, wherein the flow control information is unique to the packet on the interface during the transmission of the header and payload on the interface.

[00212] Example 64 includes the subject matter of Example 63, where the flow control information includes a Petition 870200029918, dated 09 / 24 / 2020, pp. 124 / 264 114 / 128 combination of a flow control class identifier and a virtual channel identifier for the packet.

[00213] Example 65 includes the subject matter of Example 64, in which the interface defines a maximum number of different flow control class identifier-virtual channel identifier combinations for packets sent on the interface during a given clock cycle.

[00214] Example 66 includes the subject matter of any of Examples 62 through 64, wherein the metadata for the header additionally includes parity information, header size information, and indicates whether payload data is associated with the header.

[00215] Example 67 includes the subject matter of any of Examples 51 through 66, wherein the interface additionally includes a global channel deployed using a third plurality of physical lanes, wherein the method additionally includes: communicating with the device through the global channel to perform a startup or disconnection flow for the interface.

[00216] Example 68 includes the subject matter of Example 67, in which the global channel defines a set of control signals mapped to the third plurality of physical lanes.

[00217] Example 69 includes the subject matter of Example 68, wherein the set of control signals includes a set of initialization signals for use in the initialization and disconnection flows according to an initialization state machine, and the transitions between states defined in the initialization state machine are Petition 870260029918, dated 09 / 24 / 2020, pp. 125 / 264 115 / 128 caused by the initialization signal set values.

[00218] Example 70 includes the subject matter of any of Examples 51 through 69, including additionally processing the header before the payload is completed in the data channel.

[00219] Example 71 includes the material from any of examples 51 to 70, including additionally maintaining a temporary receiver storage for credits used in the interface.

[00220] Example 72 includes the subject matter of any of Examples 51 to 71, wherein the packet is based on a Peripheral Component Interconnect Express (PCIe) protocol.

[00221] Example 73 includes the subject matter of Example 72, where the PCIe protocol includes PCIe Generation 6.

[00222] Example 74 includes the subject matter of any of Examples 51 to 73, wherein the packet is based on a Compute Express Link (CXL) protocol, and the CXL protocol includes CXL.io.

[00223] Example 75 includes the subject matter of any of Examples 51 through 74, wherein the device deploys at least a portion of an interconnect mesh of a system-on-a-chip (SoC) device, and the interface is for coupling an agent to the SoC device's interconnect mesh.

[00224] Example 76 includes material from any of Examples 51 through 75, where the device deploys a compute block of a SoC device, and the Petition 870200029918, dated 09 / 24 / 2020, pp. 122 / 264 The 116 / 128 interface is for coupling the computing block to a SoC device mesh.

[00225] Example 77 is a system that includes means to perform the method of any of Examples 51 to 76.

[00226] Example 78 includes the subject matter of Example 77, wherein the means include a set of hardware circuits.

[00227] Example 79 includes the subject matter of any of Examples 77 to 78, wherein the means include a non-transient machine-readable storage medium with instructions stored thereon, the instructions executable by a processor to cause the processor to perform at least a portion of the method of any of Examples 51 to 76.

[00228] 0 Example 80 is a method that includes: Identify a packet to be transmitted to a device through an interface; send a packet header to the device through an interface header channel, where the header channel is deployed using a first plurality of physical lanes, in which the header is sent in a first subset of the first plurality of lanes; send header metadata to the device in a second subset of the first plurality of lanes of the header channel; send packet payload data to the device in an interface data channel, where the data channel is deployed using a separate second plurality of physical lanes, and the payload data is received in a first subset of the second plurality of lanes; and send metadata of Petition 870200029918, dated 09 / 24 / 2020, pp. 126 / 264 117 / 128 payload for payload data to the device in a second subset of the second plurality of lanes.

[00229] Example 81 includes the subject matter of Example 80, including additionally: receiving header credit returns from the device in a third subset of the first plurality of lanes, wherein the header credit returns include credit returns for the header channel; and receiving data credit returns from the device in a third subset of the second plurality of lanes, wherein the data credit returns include credit returns for the data channel.

[00230] Example 82 includes the subject matter of Example 81, where header credit returns or data credit returns include shared credits.

[00231] 0 Example 83 includes the subject matter of any of Examples 80 to 82, wherein the header includes a first header of a first packet, the first header is sent in a particular clock cycle, and the method additionally includes sending a second header of a second packet in the first lane plurality in the particular clock cycle.

[00232] Example 84 includes the subject matter of Example 83, additionally including sending header metadata for the second packet in a third subset of the first lane plurality, wherein the header metadata for the first and second headers are both sent in the particular clock cycle.

[00233] Example 85 includes the subject matter of Example 83, including additionally sending, in one clock cycle. Petition 870200029918, dated 09 / 24 / 2020, pp. 128 / 264 Subsequent 118 / 128, a third header of a third packet to the device through the data channel, where the third header is loaded onto the lanes used to load the first header and a portion of the lanes used to load the second header.

[00234] Example 86 includes the subject matter of either of Examples 80 to 85, including additionally: asserting a valid header signal on a valid signal lane in the first plurality of lanes, wherein the valid header signal identifies that valid header data is sent in the first subset of the first plurality of lanes; and asserting a valid data signal on a valid signal lane in the second plurality of lanes, wherein the valid data signal identifies that valid payload data is sent in the first subset of the second plurality of lanes.

[00235] Example 87 includes the subject matter of Example 86, wherein the valid header signal is to further identify valid metadata in the second subset of the first plurality of lanes, and the valid data signal is to further identify valid metadata in the second subset of the second plurality of lanes.

[00236] Example 88 includes the subject matter of any of Examples 80 to 87, including additionally: sending a data signal start on a third subset of the second plurality of lanes deploying the data channel, wherein the data signal start indicates a payload start on the data channel, and the data signal start is sent on a clock cycle. Petition 870200029918, dated 09 / 24 / 2020, pp. 125 / 264 119 / 128 specifically to identify a first portion of the first subset of the second plurality of lanes used in the particular clock cycle to load the beginning of the payload bytes.

[00237] Example 89 includes the subject matter of Example 88, including additionally: sending an end of the data signal in a fourth subset of the second plurality of lanes that deploys the data channel, wherein the end of the data signal is sent in a subsequent clock cycle to identify a corresponding portion of the first subset of the second plurality of lanes used in the subsequent clock cycle to carry the final bytes of the payload.

[00238] Example 90 includes the subject matter of any of Examples 80 to 89, wherein the header metadata or the data metadata identifies the flow control information for the packet.

[00239] 0 Example 91 includes the subject matter of Example 90, wherein the flow control information is unique to the packet on the interface during the transmission of the header and payload on the interface.

[00240] 0 Example 92 includes the subject matter of Example 91, wherein the flow control information includes a combination of a flow control class identifier and a virtual channel identifier for the packet.

[00241] Example 93 includes the subject matter of Example 92, in which the interface defines a maximum number of different flow control class identifier-virtual channel identifier combinations for packets. Petition 870200029918, dated 09 / 24 / 2020, pp. 120 / 264 120 / 128 sent on the interface during a given clock cycle.

[00242] Example 94 includes the subject matter of any of Examples 90 to 93, wherein the metadata for the header additionally includes parity information, header size information, and indicates whether payload data is associated with the header.

[00243] Example 95 includes the subject matter of any of Examples 80 to 94, wherein the interface additionally includes a qlobal channel deployed using a third plurality of physical lanes, wherein the method additionally includes: communicating with the device through the global channel to perform a startup or disconnection flow for the interface.

[00244] Example 96 includes the subject matter of Example 95, in which the global channel defines a set of control signals mapped to the third plurality of physical lanes.

[00245] Example 97 includes the subject matter of Example 96, wherein the control signal set includes a set of initialization signals for use in the initialization and disconnection flows according to an initialization state machine, and the transitions between states defined in the initialization state machine are caused by the values ​​of the initialization signal set.

[00246] Example 98 includes the subject matter of any of Examples 80 through 97, where the packet is based on a Peripheral Component Interconnect Express (PCIe) protocol. Petition 870200029918, dated 09 / 24 / 2020, pp. 127 / 264 121 / 128

[00247] Example 99 includes the material from Example 98, where the PCIe protocol includes PCIe generation 6.

[00248] Example 100 includes the subject matter of any of examples 80 through 99, wherein the packet is based on a Compute Express Link (CXL) protocol, and the CXL protocol includes CXL.io.

[00249] Example 101 includes the subject matter of any of Examples 80 through 100, wherein the device deploys at least a portion of an interconnect mesh of a system-on-a-chip (SoC) device, and the interface is for coupling an agent to the SoC device's interconnect mesh.

[00250] Example 102 includes the subject matter of any of Examples 80 through 101, wherein the device deploys a compute block from a SoC device, and the interface is for coupling the compute block to a mesh of the SoC device.

[00251] 0 Example 103 is a system that includes means to perform the method of any of Examples 80 to 102.

[00252] Example 104 includes the subject matter of Example 103, wherein the means include a set of hardware circuits.

[00253] Example 105 includes the subject matter of any of Examples 103 to 104, wherein the means include a non-transient machine-readable storage medium with instructions stored thereon, the instructions executable by a processor to cause the processor to perform at least a portion of the method of any of Examples 80 to 102. Petition 870200029918, dated 09 / 24 / 2020, pp. 128 / 264 122 / 128

[00254] Example 106 is a system that includes: a mesh; and a plurality of compute blocks communicatively coupled across the mesh, wherein a particular compute block in the plurality of compute blocks includes: a set of agent circuits to support a load / store interconnection protocol; and a set of interface circuits to deploy an interface for coupling to a mesh, wherein the interface includes: a header channel deployed in a first subset of a plurality of physical lanes, wherein the first subset of lanes includes first lanes to load a packet header based on the interconnection protocol and second lanes to load metadata for the header;and a data channel deployed in a second, separate subset of the plurality of physical lanes, wherein the second subset of lanes includes third lanes for carrying a package payload and fourth lanes for carrying metadata for the payload.

[00255] Example 107 includes the subject matter of Example 106, wherein headers must be transmitted through the header channel in a single clock cycle, and payloads are transmissible through multiple clock cycles.

[00256] Example 108 includes the material from Example 107, where the first subset of lanes additionally includes fifth lanes for loading another header from another packet into the header channel and sixth lanes for loading metadata for the other header, the Petition 870200029918, dated 09 / 24 / 2020, pp. 129 / 264 The 123 / 128 header and the other channel must be transmitted together in a single clock cycle on the header channel.

[00257] Example 109 includes the subject matter of Example 108, in which, in a subsequent clock cycle, both the first and fifth tracks are used to carry a third header of a third package, and the size of the third header is larger than the header and the other header.

[00258] Example 110 includes the subject matter of any of Examples 106 to 109, wherein the header channel additionally includes a valid header signal in one of the first subset of lanes to identify valid header data in the first lanes, and the data channel additionally includes a valid data signal in one of the second subset of lanes to identify valid payload data in the third lanes.

[00259] Example 111 includes the subject matter of Example 110, wherein the valid header signal is to further identify valid metadata in the second lanes, and the valid data signal is to further identify valid metadata in the fourth lanes.

[00260] Example 112 includes the subject matter of any of Examples 106 to 111, wherein the second subset of lanes additionally includes five lanes to carry a data signal start to indicate a payload start on the data channel, and the data signal start is asserted on a particular clock cycle to identify a first portion of the third lanes. Petition 870200029918, dated 09 / 24 / 2020, pp. 130 / 264 124 / 128 are used in the particular clock cycle to load the beginning of the payload bytes.

[00261] Example 113 includes the subject matter of Example 112, wherein the second subset of lanes additionally includes sixth lanes to carry an end-of-signal data signal to indicate the final bytes of the payload on the data channel, and the end-of-signal data signal is asserted in a subsequent clock cycle to identify a second portion of the third lanes used in the subsequent clock cycle to carry the final bytes of the payload.

[00262] Example 114 includes the material from either of Examples 106 to 112, wherein the first subset of lanes additionally includes fifth lanes for carrying credit returns to the header channel, and the second subset of lanes additionally includes sixth lanes for carrying credit returns to the data channel.

[00263] Example 115 includes the material from Example 114, where credits for the header channel or credits for the data channel include shared credits.

[00264] Example 116 includes the subject matter of either Examples 106 through 115, wherein the metadata for the header or the metadata for the payload identifies flow control information for the packet.

[00265] Example 117 includes the subject matter of Example 116, wherein the flow control information is unique to the packet on the interface during the transmission of the header and payload on the interface. Petition 870200029918, dated 09 / 24 / 2020, pp. 135 / 264 125 / 128

[00266] Example 118 includes the subject matter of Example 117, wherein the flow control information includes a combination of a flow control class identifier and a virtual channel identifier for the packet.

[00267] Example 119 includes the subject matter of Example 118, wherein the interface defines a maximum number of different flow control class identifier-virtual channel identifier combinations for packets sent on the interface during a given clock cycle.

[00268] Example 120 includes the subject matter of any of Examples 116 to 119, wherein the metadata for the header additionally includes parity information, header size information, and indicates whether payload data is associated with the header.

[00269] Example 121 includes the subject matter of any of Examples 106 to 120, wherein the interface additionally includes a global channel deployed on a third subset of the plurality of physical lanes, wherein the global channel is for carrying control signals to the interface.

[00270] 0 Example 122 includes the subject matter of Example 121, wherein the control signals include a set of initialization signals for use in connecting and disconnecting flows to the interface.

[00271] Example 123 includes the material from Example 122, where the connection and disconnection flows conform to an initialization state machine, and the transitions between states are defined in the state machine. Petition 870200029918, dated 09 / 24 / 2020, pp. 132 / 264 Initialization errors of 126 / 128 are caused by the initialization signal set values.

[00272] Example 124 includes the subject matter of any of Examples 106 through 123, where a plurality of headers must be loaded into the header channel before payload transmission is completed.

[00273] Example 125 includes the subject matter of any of Examples 106 to 124, wherein the interface includes a first instance of the interface for sending packets to the mesh, and the system additionally includes a second instance of the interface for receiving packets from the mesh, wherein the second instance of the interface includes a second header channel and a second data channel.

[00274] 0 Example 126 includes the subject matter of Example 125, additionally includes a memory to deploy a temporary receiver storage for the second instance of the interface, wherein the temporary receiver storage supports credit sharing between flow control classes or virtual channels.

[00275] Example 127 includes the subject matter of any of Examples 106 through 126, wherein the load / store interconnect protocol includes a Peripheral Component Interconnect Express (PCIe) protocol.

[00276] Example 128 includes the subject matter of Example 127, where the PCIe protocol includes PCIe Generation 6.

[00277] Example 129 includes the subject matter of any of Examples 106 through 128, wherein the load / store interconnect protocol includes a Petition 870200029918, dated 09 / 24 / 2020, pp. 136 / 264 The 127 / 128 Compute Express Link (CXL) protocol, and the CXL protocol includes CXL.io.

[00278] Example 130 includes the subject matter of any of Examples 106 through 129, additionally including a system-on-a-chip (SoC) device, and the SoC device includes the mesh and plurality of computing blocks.

[00279] Example 131 includes the material from any of Examples 106 through 130, plus a server.

[00280] References throughout this descriptive report to “a (1) embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, occurrences of the phrases “in a (1) embodiment” or “in an embodiment” in various places throughout the descriptive report are not all necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[00281] In the preceding descriptive report, a detailed description was given with reference to specific exemplary embodiments. It will be evident, however, that various modifications and changes can be made to them without departing from the broader spirit and scope of the invention, as set forth in the appended claims. The descriptive report and the drawings should, consequently, be considered in a Petition 870200029918, dated 09 / 24 / 2020, pp. 138 / 264 128 / 128 illustrative meaning rather than a restrictive one. Furthermore, the previous use of the modality and other exemplifying language do not necessarily refer to the same modality or the same example, but may refer to different and distinct modalities, as well as potentially the same modality. Petition 870200029918, dated 09 / 24 / 2020, pp. 139 / 264

Claims

1 / 4 CLAIMS 1. Apparatus characterized in that it comprises: a first circuit block comprising a continuous transmission mesh interface, wherein the continuous transmission mesh interface maps a load / store interconnection protocol between the first circuit block and a second circuit block, wherein the continuous transmission mesh interface comprises a header channel and a data channel, wherein the first circuit block shall: send load / store interconnection protocol packet headers on the header channel, wherein the header channel comprises first lanes to carry the headers within a single clock cycle, second lanes to carry a valid first signal associated with the header channel, and third lanes to carry credit return information for the header channel;and send packet request data on the data channel, wherein the data channel comprises fourth lanes to carry the request data, fifth lanes to carry a second valid signal associated with the data channel, and sixth lanes to carry credit return information for the data channel.

2. Device, according to claim 1, characterized in that the first valid signal indicates the beginning of a new header of a new packet sent in the first lanes and the second valid signal indicates that the request data corresponding to at least one packet is sent in the fourth lanes.

3. Apparatus, according to claim 1, characterized in that credit returns for the header channel are made to a first credit pool comprising dedicated credits and shared credits for the header channel, and credit returns for the data channel are made to a first credit pool comprising dedicated credits and shared credits for the data channel.

4. Apparatus, according to claim 1, characterized in that the continuous transmission mesh interface further comprises seventh lanes for carrying header metadata to the headers, and the header metadata comprises header size, flow control, virtual channel and parity information.

5. Apparatus, according to claim 1, characterized in that the continuous transmission mesh interface further comprises a global channel implemented in the seventh lane for carrying signals for use in the initialization and shutdown of the continuous transmission mesh interface.

6. Device according to claim 1, characterized in that a plurality of headers must be sent on the first lane within a single clock cycle, and the plurality of headers comprises a single header.

7. Apparatus, according to claim 1, characterized in that the continuous transmission mesh interface comprises a first instance of continuous transmission mesh interface for sending packets from the first circuit block to the second circuit block, and the apparatus comprises a second instance of continuous transmission mesh interface for receiving packets in the first circuit block from the second circuit block, wherein the first and second instances of continuous transmission mesh interface comprise respective instances of the header channel and the data channel.

8. Device according to claim 1, characterized in that the charging / storage interconnection protocol is based on a Peripheral Component Interconnect Express (PCle) based protocol.

9. Device according to claim 1, characterized in that the loading / storage interconnection protocol is based on a Compute Express Link (CXL.io) input / output protocol.

10. A method characterized by the fact that it comprises: identifying a set of packets to be sent over an interconnection; sending the set of packets from an application layer block to a controller block through a continuous transmission mesh interface, wherein the continuous transmission mesh interface comprises a header channel comprising a first set of lanes and a data channel comprising a second set of lanes, wherein the sending of the set of packets from the application layer block to the controller block comprises: sending a valid header signal on valid header lanes in the first set of lanes; sending headers, within a single clock cycle, to the set of packets on header lanes in the first set of lanes; sending header information on header information lanes in the first set of lanes; sending a valid data signal on valid data lanes in the second set of lanes;and Petition 870260059427, dated 06 / 18 / 2026, page 15 / 17 3 / 4 send packet set request data in data lanes in the second set of lanes; receive credit return information associated with the header channel in a header credit return lane in the first set of lanes; and receive credit return information associated with the data channel in a data credit return in the second set of lanes.

11. A method according to claim 10, characterized in that the packet set comprises a plurality of packets, and a plurality of headers associated with the plurality of packets are sent on the header lanes in a single clock cycle.

12. Method, according to claim 11, characterized in that a first valid lane in the valid lanes of the header indicates the sending of a first header from the plurality of headers and a second valid lane in the valid lanes of the header indicates the sending of a second header from the plurality of headers.

13. A method according to claim 10, characterized in that the packet set comprises transaction layer packets (TLPs) of a load / store protocol.

14. A system characterized in that it comprises: a mesh; and a computing block comprising: an interface for mesh coupling, wherein the interface comprises a header channel and a data channel; and agent circuits for supporting a load / store interconnection protocol, wherein the agent circuits are for an interface for mesh coupling, wherein the interface comprises: sending load / store interconnection protocol packet headers on the header channel, wherein the header channel comprises first lanes for carrying the headers within a single clock cycle, second lanes for carrying a valid first signal associated with the header channel, and third lanes for carrying credit return information for the header channel;and send packet request data on the data channel, wherein the data channel comprises fourth lanes to carry the request data, fifth lanes to carry a second valid signal associated with the data channel, and sixth lanes to carry credit return information for the data channel.

15. System according to claim 14, characterized in that it comprises a plurality of computing blocks, wherein the mesh interconnects the plurality of computing blocks in the system.

16. System according to claim 15, characterized in that the system comprises a system-on-a-chip (SoC) and the SoC comprises the mesh and plurality of computing blocks.

17. System according to claim 15, characterized in that the system comprises a server.

18. System according to claim 14, characterized in that the interface comprises a first interface for sending data from the computing block to the mesh, and the computing block further comprises a second interface for receiving data from the mesh, wherein the second interface comprises a respective header channel and a data channel for packets to be sent from the mesh to the computing block.

19. System according to claim 14, characterized in that the load / store interconnect protocol comprises one of the PCIe or CXL.io protocols.

20. System, according to claim 14, characterized in that the interface further comprises a global channel implemented in seven lanes to carry signals for use in the initialization and shutdown of the interface. Petition 870260059427, dated 06 / 18 / 2026, p. 17 / 17

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